Dr. Jeff Gambino

Tutorial Title: BEOL Reliability;  from FinFETs to More-than-Moore Devices

This tutorial will provide a brief overview of Back-End-Of-Line (BEOL) reliability.  The first part of the tutorial will cover basic reliability statistics and test methods for electromigration, stress migration, time-dependent dielectric breakdown, and chip-package interaction (CPI).  The next part will describe key interconnect reliability issues for 14nm node and beyond technology nodes, focusing on electromigration, TDDB, and CPI for these nodes.   The third part will address unique reliability challenges for 3D integration, focusing on reliability of through-silicon vias (TSVs) and the effects of thin die on mechanical reliability and on device reliability. The final part of the tutorial will address BEOL reliability issues for More-than-Moore devices, including automotive devices, power devices, RF devices, and sensors.

Dr. Philippe Perdu

Tutorial Topic: SiP, Packaged stacked devices and other challenging 3D assembly analysis

3D devices technologies allow cost reduction, performance boost and more and more functionalities integration:

– Systems in Package (SiP) embed heterogeneous technologies (sensors, RF, power, analog, and digital);

– IC Manufacturers stack dies to target incredible storage (FLASH) or computation (FPGA) capacities while through Silicon Vias (TSV) open the door to very short and fast interconnections. In order to optimize design and process while assessing quality and reliability, failure analysis of failed part is a key to improve design and process as it gives the opportunity to set up efficient and cost effective corrective actions. Unfortunately, 3D Failure analysis is quite challenging. A third dimension has been added to what we previously had, optical access is very limited while 3D device complexity and heterogeneity trigger the need of having new specific approaches for these devices. Sample preparation is another challenge to access parts of the device to analyse while maintaining its electrical behaviour.

This tutorial will focus on 3D devices Failure Analysis defect isolation and localization. Only few physical principles can be used when we do not have direct optical access inside the device: thermal wave, electromagnetic field (magnetic field, reflectometry), X Ray and acoustic wave. Defect localization is done by techniques that link the abnormal electric behaviour (for instance short circuit) with a localized part. It can be completed by imaging tools able to pinpoint delamination, cracks (acoustic) or shorts and wide open (X-ray). These imaging techniques are also very useful along the FA process and can be enough for some basic failures.

I will give attendees a brief overview of chip access and some background on defect localization techniques, from physical principles to applications. It concerns Observation tools (Optical, Acoustic, X-Ray) and Tools and techniques directly correlated with electrical diagnosis (TDR and EOTPR, Thermography, Magnetic Microscopy). In addition, I will present Complementary or Emerging tools and techniques: TeraHertz Imaging, Thermoreflectance, Magneto-Optical Frequency Mapping (MOFM) …


Describing these techniques is not enough, it is important to learn if a specific technique is suitable regarding electrical diagnosis and to choose the most appropriate. These points will be inside the tutorial technique by technique and it will be summarized by brief guidelines to setup the best defect localization technique accordingly. This tutorial will end with a full 3D case study done in our lab.

Dr. Robin Degraeve

Tutorial Topic: Intrinsic Reliability Challenges for Non-Volatile Memory Technologies

This tutorial aims at giving an overview of the physics-related, intrinsic reliability issues in memory devices. Both conventional memories, like flash and sonos, as well as potential alternative memories like resistive RAM and MRAM are considered. The tutorial starts from a fundamental defect-centric picture and from generally applicable statistical insights. It studies the formation and impact of dielectric defects on measurable characteristics like read current window, retention, etc… In this way, the fundamental insights from material sciences are projected to the reliability at the device level. This allows us to comprehensively discuss the consequences for the continuous scaling effort. The tutorial presents an overview of reliability risks in alternative memories and speculates on possible reliability issues in exploratory memories. Finally, the impact of reliability issues for new potential memory applications like neuromorphic networks are critically analyzed.

Michel Bosman

Michel Bosman is Associate Professor at the National University of Singapore and a Scientist at the A*STAR Institute of Materials Research and Engineering in Singapore, specializing in scanning transmission electron microscopy (STEM).

He is trained at Delft University of Technology (the Netherlands) and at the University of Sydney, with postdoctoral experience in Australia, the UK and Singapore. His research focuses on nanoscale sample characterization using electron spectroscopy and on the development of experimental nano-optical techniques in the STEM, such as monochromated electron energy-loss spectroscopy (EELS).

Tutorial Topic: Physical Analysis with the TEM – Possibilities and Challenges

This tutorial will give a layman’s introduction to electron microscopy, followed by a discussion of ‘What can and cannot currently be done with TEMs’. Various TEM-based imaging and spectroscopy techniques will be discussed, with examples from physical and semiconductor device analysis.

State-of-the-art TEM and scanning TEM (STEM) instrumentation will be introduced, as well as the new characterisation capabilities they bring.

Michél Simon-Najasek

Tutorial Topic: Defect localization using SEM based current imaging

Within the last year’s current imaging techniques used in scanning electron microscopy (SEM) are more and more applied for visualization of dopant structures and metal networks including precise localization of electrical defects in integrated circuits. Two different techniques are available, firstly the EBIC method (electron beam induced current) and secondly the EBAC method (electron beam absorbed current) which is also known as RCI (resistive current imaging). For both methods the primary electron beam of the SEM acts as a local current source generating a resulting current density within the IC structure. This current is gripped by probe needles at certain IC positions, is subsequently amplified and finally synchronized with the SEM image. As a result the acquired current image can directly be correlated to the IC structure of the sample under investigation.

The EBIC method is commonly used to investigate pn junctions of diodes in planar and vertical direction to get information about the position and the size of the depletion zone and to verify dopant process parameters. Here the induced current is measured which is cause by electron hole pair generation and separation by the in-built electrical field of the pn-junction. In addition, by applying an external biasing the EBIC current and size of the depletion zone can be influenced.

The EBAC method allows the localization of opens and shorts within the metal network. It uses the electron probe current which is absorbed by a metallization line and measured by a probe needle at a certain position of the metal network under investigation. The current paths can directly be imaged, thus, opens and shorts can easily be extracted from the EBAC image in relation to the layout or reference devices. Furthermore a recently developed approach allows the localization of thin oxide shorts or weaknesses by EBAC as well. For this application EBAC can be seen as a complementary approach to Photoemission Microscopy (PEM) due to its higher sensitivity and lateral resolution.

The tutorial will discuss basics and advanced approaches of EBIC / EBAC imaging within an SEM and demonstrate their applications by selected case studies.  Furthermore recently introduced application electron beam induced resistance change (EBIRCH) technique will be discussed.

Prof. Aaron Thean

Aaron Thean is a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS), since May 2016. His current research interests involve Heterogeneous Integration of Nano-systems and Hybrid-Flexible Electronics. He is the Director of NUS’ new central Nanofabrication Center. Besides his NUS responsibilities, Aaron serves on the Scientific Advisory Board for the NUS-MIT research alliance SMART-LEES, A*Star IME, and Huawei Singapore Research Center.  He is currently an Editor of IEEE Electron Device Letters. Prior to his transition to NUS, Aaron was the Vice President of Logic Technologies and the Director of the Logic Devices Research at IMEC. From 2011 to 2016, he directed the research and development of device technologies ranging from ultra-scaled FinFETs to III-V/Ge Channels, emerging nano-device architectures, logic spintronics, and novel materials.  Before 2011, Aaron was with Qualcomm’s CDMA technologies in San Diego, California. Before Qualcomm, Aaron was the Device Manager at IBM East Fishkill New York, where he led his team to develop the industry’s first gate-first metal-gate 28-nm and 32-nm low-power bulk CMOS technologies. The technology was successfully commercialized by IBM’s foundry partners and enabled some of today’s most successful mobile devices.  Aaron started his industry career at Freescale Semiconductor (and Motorola) where he did research on many novel devices that included Strained-Si-On-Silicon, FinFETs, FDSOI, and Nanocrystal Flash Memory. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc (Highest Honors), M.Sc, and Ph.D  degrees in Electrical Engineering.  He has published over 300 technical papers and holds more than 50 US patents. Among his notable recognitions, he and his IMEC team received the 2014 Compound Semiconductor Industry Innovation award for their IIIV FinFET work. Aaron returned to Singapore in 2016 to receive the National Research Foundation (Singapore)’s Returning Singapore Scientist Award and started his career in academia.

Tutorial Topic: FinFET & Post-FinFET Advanced Logic Device Reliability– A Review

Over the last decade, CMOS logic technologies have incorporated several material disruptions. Advanced CMOS made the transition from Poly-SiON to High-k metal gate (HKMG) process about 10 years ago, for 45nm and 32nm/28nm planar CMOS transistors developed from 2007 to 2009, respectively. The efforts to bring these technologies to high-volume manufacturing accelerated our learning on gate-stack reliability, especially the role of thermal budget management on the replacement metal-gate process. There are major influences of gate PBTI and NBTI due to the device integration scheme like dopant activation and silicidation. For example, “high-k-first” and “high-k-last” gate stacks showed different reliability potentials. However, with process and integration schemes, we found solutions to engineer both stacks to meet requirements.

The next disruption came quickly as we transitioned from planar to FinFET technologies in 2011, with Intel’s 22nm CMOS. This coincided with the capabilities of Atomic Layer Deposition (ALD) technologies for the the HKMG process. The lessons learnt on managing BTI impact did carried forward, but we now contend with new influences due to a different dielectric-crystalline interface of the fin sidewalls and the process challenges of a largely vertically oriented gate structure.  We saw that ALD material improvements helped us overcome some of the issues. However, with increased current densities and aggressive dimensional scaling, hot-carrier and device self-heating rose to top of the issue list. Following the current success of 14nm/16nm FinFET technologies, we will soon be seeing the 3rd generation FinFET technologies with upcoming10nm and 7nm CMOS, in the coming two years. However, there are still really few knobs to overcome these top issues at the material or process levels. Except, at the circuit design or system levels through engineering the use conditions.

The next disruptions may come at or after 5nm CMOS targeted for 2020. With the need for more performance, new materials like SiGe fins are being considered for integration, or stacked Nanowires. We see exciting new reliability understanding and opportunities brought forth with these new materials and structures. Beyond FinFETs and beyond Si, we will need to prepare for low-thermal budget processes (E.g. for III-V, Ge). Encouragingly in recent years, we have gained significant new insights towards reliable low-thermal budget gate stacks. This will pave the way needed to realize the integration of these new materials for the Fin or Nanowire devices. In this presentation, we will review this evolution of understanding in reliability physics driven by this relentless revolution of device and material architectures to continue Moore’s law.

Prof. Christian Bolt

Tutorial Topic: Internet of Things and Low Power – Technology Concepts and Fault Isolation on Chip and System Level

Internet of (Every)Thing(s), cloud computing and other new application fields of electronic devices require a rapid transition to high data rate processing, forcing clock speeds well into the 100GHz regime soon. This vision reflects a performance progress much faster than Moore’s 2D law would imply. On top of that, Moore’s law is quite under pressure because further miniaturization is not anymore accompanied by cost reduction.

The central theme of the tutorial is the challenge of coming technologies for Contactless Fault Isolation (CFI). It covers how Visible CFI techniques are covering the image resolution in the light of the latest ITRS roadmap 2D scaling relaxations.

It will then discuss 3D integration on system level with Through Silicon Vias (TSVs) and on chip level with Gate All Around (GAA) devices. A perspective into photonic interconnects, new test concepts and security issues will be given.

A special chapter will present CFI challenges with low power technologies. Photon emission can make an interesting contribution using longer wavelengths in order to get a higher signal for low power. Spectral photon emission gives access to new device performance parameters derived from the “electron temperature” in the FET channel. This is now detectable with a very small error margin and – for that reason – usable for debug and FA. Such a concept may close the gap between visible CFI and lock in thermography.

This tutorial will be concluded with a vision how challenges may be turned into chances.

Steven Herschbein

Tutorial Topic: Focused Ion Beam (FIB) Chip Circuit Edit Tutorial

Focused Ion Beam (FIB) tools have become a mainstay of the modern semiconductor Failure Analysis (FA) laboratory. The FIB is the tool of choice for a wide range of lab activities, including chip circuit edit and design debug, advanced electrical fault isolation, logical-to-physical verification, stress-free cross sectioning, and sample preparation for a wide variety of other analysis activities. As such, a properly configured FIB tool can be invaluable in reducing yield learning cycles and speeding product time-to-market.

While we will touch on a number of subjects and use cases, the main intent of this tutorial is to provide an overview of some of the most common ‘electrically oriented’ FIB applications, with emphasis on the following:

  1. Resolving the Business Case Question: Why do FIB Chip Circuit Edit?
  2. A look at the Chip Edit FIB tool configuration, beam parameters and the various process gases available.
  3. Examine the sample preparation changes and the new tooling made necessary by the evolution of semiconductor packaging. We’ll review full silicon thickness, locally thinned and global ultra-thin contour milling as an edit starting point.
  4. Circuit edit and design/layout basics: metal & dielectric etch, copper vs aluminum, front & backside access, navigation & endpointing, charge control, standard bulk CMOS & SOI device construction, planar & FinFET devices.
  5. The changing landscape: shrinking geometries, vertical device integration, chip stacking, and the need for designs/layout that better enable editing success.
  6. Alternative ion FIB tools (He, Ne, Xe, etc.) and e-beam processing, the multi-beam FIB advantage, & considerations for future edit tools.
  7. FIB probe pads & in-situ probing for SRAM cell & circuit characterization, an introduction to Passive Voltage Contrast (PVC) and other fault isolation techniques.
  8. Attempts to migrate some laboratory FIB techniques into the wafer Fab line.
  9. A few examples to tie the various techniques together.