Call for Papers

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Call for Papers

IPFA 2018 is devoted to the fundamental understanding of the electrical and physical characterization techniques and associated technologies that assist in probing the nature of wear-out and failure in conventional and new CMOS devices, in turn resulting in improved knowhow of the physics of device / circuit / module failure that serves as critical input for future design for reliability.

The Technical Program Committee is inviting papers related, but not limited to, the following areas:

Sample Preparation, Metrology and Defect Characterization
Device deprocessing; Ion beam/TEM sample preparation; metrology inline inspection;  test chips.

Case Studies on Fault Isolation
Die/Board/System-level electrical FA; Electrical characterization and nanoprobing;  Hardware security.

Case Studies on Physical Failure Analysis
Die/Board/System-level physical FA; Design for manufacturing; Construction Analysis; Reverse engineering.

Package-Level Failure Analysis
2.5D/3D Package FA; Magnetic/acoustic applications; 2D/3D X-ray;  FTIR; non-destructive failure analysis.

Advanced Electrical Fault Isolation Techniques
Advanced methodologies in emission microscopy, Lock-in thermography, Laser timing techniques, Acoustic microscopy, Magnetic imaging, Software-based techniques.

Advanced Physical Failure Analysis Techniques
Advanced methodologies in nanoprobing, AFP, EBAC/EBIC, Advanced optical beam, Ion Beam, Magnetic, scanning probe based techniques.

Device Reliability
Gate oxide/High-κ Reliability, PBTI/NBTI, Hot carrier, Random Telegraph Noise and Single dopant effects, Self Heating in Sub-16 nm. Process and stress-induced variability, ESD/EOS Failures and Radiation effects; circuit/ system level analysis of performance variability, reliability of non-silicon devices, Non-volatile memory (NVM) reliability.

Interconnect and Packaging Reliability
TDDB in low-κ dielectrics, Electromigration, stress migration, process and stress-induced variability in interconnect, cracking, corrosion, and fatigue in bond pads; Reliability in 3DICs and TSVs, Thermomechanical stress and power dissipation issues, wire bonding, die attach and encapsulation issues, wafer bonding technology, yield and reliability.


Timeline

  • Draft Full Paper Submission Due – MAY 20
  • Mentor Feedback on Draft Full Paper – JUNE 5
  • Final Paper Submission Due – JUNE 20
  • Presentation Slides / Poster Materials Due – JULY 5