Speakers

Invited

Speakers

Christian Schmidt

Invited Talk Topic: From PCB to BEOL: 3D X-Ray Microscopy for Advanced Semiconductor Packaging

Dr. Christian Schmidt received a diploma in physics technology and data information from the University of Applied Science Merseburg, in 2007 and the PhD degree in engineering from Martin-Luther University Halle-Wittenberg, Germany, in 2013.

 

From 2007 to 2012 he was a failure analysis engineer and research fellow at the Fraunhofer Institute for Mechanics of Materials, Halle Germany.He joined DCG Systems as SR. APPLICATION DEVELOPMENT ENGINEER in 2012 before he became a MEMBER OF TECHNICAL STAFF and later SR. SECTION MANAGER FOR PACKAGE FAILURE ANALYSIS at Globalfoundries Fab 8, Malta, New York.In 2016 he joined Carl Zeiss SMT as SOLUTIONS MANAGER FOR ADVANCED SEMICONDUCTOR PACKAGING.

 

He has authored over 30 publications including international conferences and journals and holds 3 patents. Dr. Schmidt has received the ISTFA Outstanding Paper Award in 2010 and the ECTC Best Paper Award in 2011.

Christine Hau

Invited Talk Topic: Electromigration Reliability of Solder Balls

Christine Hau-Riege has 18 years of experience in the semiconductor industry, focusing on device and package-level reliability.  Currently, she is a Principal Engineer in Qualcomm’s reliability team.  She has previously held similar positions at Intel and AMD.  She received her B.S. and Ph.D. degrees in the department of material science and engineering at MIT in 1996 and 2000, respectively.  She is also active in conferences such as IRPS and ECTC.  She is the first-author of about 20 publications and holds 19 US patents.

Dr. Jeff Gambino

Invited Talk Topic: BEOL Reliability for More-than-Moore Devices

Dr. Gambino received the B.S. degree in materials science from Cornell University, Ithaca, NY, in 1979, and the PhD degree in materials science from the Massachusetts Institute of Technology, Cambridge, MA, in 1984.  He joined IBM in 1984.  While there, he worked on process integration and reliability for silicides, DRAM, copper interconnects, CMOS image sensors, RF devices, and Through-Silicon Vias.  He joined ON Semiconductor, Gresham, OR, in 2015.  He is currently working on process integration and reliability for CMOS image sensors and high voltage semiconductors. He has published over 200 technical papers and holds over 500 patents.

Tutorial Title: BEOL Reliability;  from FinFETs to More-than-Moore Devices

This tutorial will provide a brief overview of Back-End-Of-Line (BEOL) reliability.  The first part of the tutorial will cover basic reliability statistics and test methods for electromigration, stress migration, time-dependent dielectric breakdown, and chip-package interaction (CPI).  The next part will describe key interconnect reliability issues for 14nm node and beyond technology nodes, focusing on electromigration, TDDB, and CPI for these nodes.   The third part will address unique reliability challenges for 3D integration, focusing on reliability of through-silicon vias (TSVs) and the effects of thin die on mechanical reliability and on device reliability. The final part of the tutorial will address BEOL reliability issues for More-than-Moore devices, including automotive devices, power devices, RF devices, and sensors.

Dr. Jin Ju Kim

Invited Talk Topic: Reliability assessment of 10nm FinFET process technology.

Jin Ju Kim is senior quality and reliability engineer in Technology Q&R group, Foundry Business, Samsung Electronics in Korea since 2014. She is responsible for 10/14 FEOL reliability assessment which includes process evaluations, generating physical models for circuit reliability process design kit (PDK), and conducting process qualifications. She received Ph.D. degree in Nanobio Materials and Electronics from the Gwangju Institute of Science and Technology (GIST), Gwangju, Korea in 2014. She’s published more than 30 papers in the field of semiconductor and high-k reliability. Her research interest includes the physical reliability mechanism and modeling on high-k/metal gate stack technologies, as well as FinFET devices.

Dr. Philippe Perdu

Invited Talk Topic: Failure Analysis on Space Electronics: Best Practices, Challenges and Trends

Philippe Perdu is Senior Expert in microelectronics at CNES. He has led the VLSI Failure Analysis CNES laboratory since 1988. His main activity is to develop techniques and to adapt tools for electronic components dedicated to space applications. It mostly concerns FA process (defect localization).

His other activities are to provide support to space project (failure analysis at system / board / component level), to drive expertise roadmap (tooling) and to setup R&D programs related to VLSI expertise and reliability, to coach, train and supervise teams dedicated to these activities.

He holds an Electronic Specialty MS, Ph.D. and HDR (academic research supervisor). He has authored or co-authored more than 239 papers and 25 patents.

He chaired CCT MCE, a corporate network on electronic components and MEMS (2007 to 2011) and ANADEF, the French FA society (former president from 2005 to 2009, now secretary). He has been board member of EDFAS (Electron Device Failure Analysis Society), Organizing Committee member of ISTFA from 2005 to 2014 (Technical Chair in 2010, General Chair in 2012). He is still EUFANET (European Failure Analysis NETwork) board member, Associate Editor of EDFA Magazine, Editorial Advisory Board member of Miroelectronics Reliability and Steering Committee member of ESREF (Vice-Chair in 2015). He has participated in ESREF, ISTFA, IRPS, IPFA conferences as author, committee member and session chair.

He his doing research on optical testing (static and dynamic laser stimulation, laser probing and emission microscopy) and defect localization in 3D devices.

He is deeply involved in CNES / NTU cooperation and Adjunct Senior Principal Research Scientist at Temasek laboratories @ NTU since 2016 and Intraspec Technologies Scientific Advisor since 2011.

Tutorial Topic: SiP, Packaged stacked devices and other challenging 3D assembly analysis

3D devices technologies allow cost reduction, performance boost and more and more functionalities integration:

– Systems in Package (SiP) embed heterogeneous technologies (sensors, RF, power, analog, and digital);

– IC Manufacturers stack dies to target incredible storage (FLASH) or computation (FPGA) capacities while through Silicon Vias (TSV) open the door to very short and fast interconnections. In order to optimize design and process while assessing quality and reliability, failure analysis of failed part is a key to improve design and process as it gives the opportunity to set up efficient and cost effective corrective actions. Unfortunately, 3D Failure analysis is quite challenging. A third dimension has been added to what we previously had, optical access is very limited while 3D device complexity and heterogeneity trigger the need of having new specific approaches for these devices. Sample preparation is another challenge to access parts of the device to analyse while maintaining its electrical behaviour.

This tutorial will focus on 3D devices Failure Analysis defect isolation and localization. Only few physical principles can be used when we do not have direct optical access inside the device: thermal wave, electromagnetic field (magnetic field, reflectometry), X Ray and acoustic wave. Defect localization is done by techniques that link the abnormal electric behaviour (for instance short circuit) with a localized part. It can be completed by imaging tools able to pinpoint delamination, cracks (acoustic) or shorts and wide open (X-ray). These imaging techniques are also very useful along the FA process and can be enough for some basic failures.

I will give attendees a brief overview of chip access and some background on defect localization techniques, from physical principles to applications. It concerns Observation tools (Optical, Acoustic, X-Ray) and Tools and techniques directly correlated with electrical diagnosis (TDR and EOTPR, Thermography, Magnetic Microscopy). In addition, I will present Complementary or Emerging tools and techniques: TeraHertz Imaging, Thermoreflectance, Magneto-Optical Frequency Mapping (MOFM) …

 

Describing these techniques is not enough, it is important to learn if a specific technique is suitable regarding electrical diagnosis and to choose the most appropriate. These points will be inside the tutorial technique by technique and it will be summarized by brief guidelines to setup the best defect localization technique accordingly. This tutorial will end with a full 3D case study done in our lab

Dr. Robin Degraeve

Invited Talk Topic: Intrinsic reliability challenges for non-volatile memory technologies.

Robin Degraeve is currently a Principal Scientist at imec, Belgium. He received the M.Sc. degree in electrical engineering from the University of Ghent, Belgium, in 1992 and the Ph.D. degree from KULeuven, Belgium, in 1998. In 1992, he joined imec, Leuven, in the Device Reliability and Characterization Group. His work has been focusing on the reliability aspects of thin insulating layers under electrical stress. His current research interests include the physics of degradation and breakdown phenomena in gate oxide films, the reliability of flash memory devices and the characterization and the reliability of high-k materials as gate insulators for future CMOS generations and memory applications. Later, he has been working mainly on Resistive RAM memory development and modeling. He is currently involved in the exploration of Resistive RAM for machine learning purposes.

Tutorial Topic: Intrinsic Reliability Challenges for Non-Volatile Memory Technologies

This tutorial aims at giving an overview of the physics-related, intrinsic reliability issues in memory devices. Both conventional memories, like flash and sonos, as well as potential alternative memories like resistive RAM and MRAM are considered. The tutorial starts from a fundamental defect-centric picture and from generally applicable statistical insights. It studies the formation and impact of dielectric defects on measurable characteristics like read current window, retention, etc… In this way, the fundamental insights from material sciences are projected to the reliability at the device level. This allows us to comprehensively discuss the consequences for the continuous scaling effort. The tutorial presents an overview of reliability risks in alternative memories and speculates on possible reliability issues in exploratory memories. Finally, the impact of reliability issues for new potential memory applications like neuromorphic networks are critically analyzed.

Frank Altmann

Invited Talk Topic: Failure Analysis Techniques for 3D Packages

Frank received his Diploma in Physics from the Technical University, Dresden. In 1997 he started at Fraunhofer as scientist for electron microscopy and FIB working on failure analysis for integrated circuits. Since 2006 he has been working as head of the research group »Diagnostics of semiconductor technologies« at the Fraunhofer Institute for Microstructure of Materials and Systems. His team is dealing with the development of novel techniques for focused ion beam sample preparation, SEM based current and active dopant contrast imaging and lock-in thermography defect localization. Furthermore, Frank works on advanced failure analysis techniques for 3D packages and holds patents for 3D LIT approaches. He has authored and co-authored more than 60 publications and is co-organizer of the European FIB Workshops EUFN and EFUG. Since 2012 he has been organizing the International CAM Workshop on Innovations in Failure Analysis and Material Diagnostics of Electronics Components. In 2016 he acted as technical program chair for the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis Conference (ESREF).

 

Liu Binghai

Invited Talk Topic: The Overview of the Impact of Electron Radiation on Semiconductor Failure Analysis by SEM, FIB and TEM

 

Binghai currently is a senior member of technical staff in product FA, Globalfoundries SGP. Before joining Globalfoundries SGP, he worked as the TEM facility manager in Center of Bioimaging Science in the National University of Singapore. Binghai has more than 20 years experience in TEM, and he has authored and co-authored more than 40 journal publications and around 20 conference papers in the field of semiconductor failure analysis and materials science.

Mario Lanza

Invited Talk Topic: Reliability of Layered Dielectrics studied via Conductive Atomic Force Microscopy

 

Mario Lanza is a Young 1000 Talent Full Professor at Soochow University. Dr. Lanza got his PhD in Electronics in 2010 at Universitat Autonoma de Barcelona, and two postdocs, one at Peking University (2010-2011) and another one at Stanford University (2012-2013). He has published over 80 papers (including Science), edited a book for Wiley-VCH and registered four patents (one of them received 1M$ investment). He is member of the advisory board of Advanced Electronic Materials, Scientific Reports and Nanotechnology, and member of the technical committee of several international conferences. His research interests focus on the improvement of electronic devices using 2D materials, with special emphasis on 2D (layered) dielectrics and logic memory devices.

Michél Simon-Najasek

Invited Talk Topic: Application of the SEM-EBAC technique for defect localization in thin dielectrics

Michél Simon-Najasek is a senior FA engineer at the Fraunhofer IMWS / CAM in Halle, Germany where he leads the team physical failure analysis. He received his Bachelor of European Engineering at the University of Coventry in 2001 and his diploma in electrical engineering at the University of Applied Science in Koethen / Germany in 2002. For more than 14 years he has been working in the research group „Diagnostic of semiconductor technologies” at Fraunhofer. Michél´s research field is failure analysis on Si and III/V based electronic devices mainly for automotive applications. He is expert in focused ion beam preparation, electron microscopy analysis and nanoprobing in connection with current imaging methods for IC level diagnostics.

Tutorial Topic: Defect localization using SEM based current imaging

Within the last year’s current imaging techniques used in scanning electron microscopy (SEM) are more and more applied for visualization of dopant structures and metal networks including precise localization of electrical defects in integrated circuits. Two different techniques are available, firstly the EBIC method (electron beam induced current) and secondly the EBAC method (electron beam absorbed current) which is also known as RCI (resistive current imaging). For both methods the primary electron beam of the SEM acts as a local current source generating a resulting current density within the IC structure. This current is gripped by probe needles at certain IC positions, is subsequently amplified and finally synchronized with the SEM image. As a result the acquired current image can directly be correlated to the IC structure of the sample under investigation.

The EBIC method is commonly used to investigate pn junctions of diodes in planar and vertical direction to get information about the position and the size of the depletion zone and to verify dopant process parameters. Here the induced current is measured which is cause by electron hole pair generation and separation by the in-built electrical field of the pn-junction. In addition, by applying an external biasing the EBIC current and size of the depletion zone can be influenced.

The EBAC method allows the localization of opens and shorts within the metal network. It uses the electron probe current which is absorbed by a metallization line and measured by a probe needle at a certain position of the metal network under investigation. The current paths can directly be imaged, thus, opens and shorts can easily be extracted from the EBAC image in relation to the layout or reference devices. Furthermore a recently developed approach allows the localization of thin oxide shorts or weaknesses by EBAC as well. For this application EBAC can be seen as a complementary approach to Photoemission Microscopy (PEM) due to its higher sensitivity and lateral resolution.

The tutorial will discuss basics and advanced approaches of EBIC / EBAC imaging within an SEM and demonstrate their applications by selected case studies.  Furthermore recently introduced application electron beam induced resistance change (EBIRCH) technique will be discussed.