Invited Papers


Baozhen Li

Baozhen Li is a Senior Technical Staff Member (STSM) at IBM Systems. He has been working on technology reliability for more than 20 years.  His experiences cover a wide range of reliability aspects, including electromingttion (EM), stress migration (SM), dielectric breakdown (TDDB), thermal mechanical stability and chip-package interactions (CPI). In addition to reliability studies for leading edge semiconductor technology development, he also works on reliability design optimization and chip level reliability for high end computing systems.  He publishes and patents extensively in the semiconductor technology and reliability area.  He has given multiple tutorials and invited talks at international conferences and wrote multiple invited introductory papers in journals. He received a bachelor’s degree from Northeastern University in China and Ph. D degree from the University of Notre Dame in USA.

Invited Talk Topic: Advanced On-Chip Interconnect Reliability

For high performance computing applications, the on-chip interconnect not only needs to carry high electrical current and support high Vmax devices, but also must sustain extremely low reliability failure during long product lifetime.  To meet these challenges, a good understanding of translating element reliability to system level reliability is essential.  In this talk, discussions will be made on reliability failure characteristics and statistics from simple elements to more complicated systems.   Examples will be given on electromigration (EM) failure probability from a simple via/line structure to on chip power grid, including how the redundancy and current redistribution impacts EM lifetime and failure statistics.  Details will also be discussed on  thermal interactions among the neighboring elements and their impact on reliability failure and scaling.

Bin Gao

Bin Gao is an associate professor with the Institute of Microelectronics, Tsinghua University, Beijing, China. He received the B.S. degree in physics in 2008 from Peking University, Beijing, China, and received the Ph.D. degree in microelectronics from Peking University in 2013. He joint Tsinghua University in 2015. His research interests focus on optimization, characterization and modelling on oxide based RRAM.

Invited Talk Topic: Reliability Assessment for Oxide based Neuromorphic Devices and Systems

A perspective is provided to compare the reliability requirements of metal oxide based Resistive Random Access Memory (RRAM) for digital memory application and neuromorphic computing application. Retention and endurance are considered as the two key device metrics to evaluate the impact on neuromorphic system. Statistical measurements and system simulation demonstrate that the retention and endurance degradation behaviors of oxide based RRAM are quite unique when implementing on a neuromorphic system. New evaluation method is therefore needed for reliability assessment.

Ching-Chun Lin

Ching-Chun Lin is a deputy manager at the TEM sample preparation section at the integrated Service Technology Inc (iST). His daily job includes management and development of TEM related activity, such as dual-beam FIB, TEM/STEM, NBD, EDX and EELS analysis. Prior to joining iST, he was a principal engineer at Taiwan Semiconductor Manufacturing Company Limited (TSMC), Hsinchu, Taiwan from 2013 to 2014. His work in TSMC mainly focused on the 16nm Backend of line (BEOL) process integration. He received B.S. degree in chemical engineering in 2006, and Ph.D. in material science in 2012 from Tsinghua University, Hsinchu, Taiwan.

Invited Talk Topic: Failure Analysis for Advanced Package Technology

In this talk, the methodology of failure analysis for advanced package technology, such as 3D IC, InFO and CoWos structures is provided. Different failure modes are reported using variety of fault isolation tools. We try to establish the successful pattern to improve the fault isolation based on our experience, which will be discussed in this presentation as well.

Christian Boit

Christian Boit was Chair of Semiconductor Devices at Technische Universität Berlin from 2002 to 2018, prior to that Director of Failure Analysis at Infineon Technologies AG, Munich, Germany. He was involved in infrared based contactless characterization of electronic devices from 1983, a pioneer of photon emission for Siemens AG 1988 and protagonist of chip backside access techniques from 1996 on. He published more than 150 papers and supported the major conferences of this topic. He was a founding member of EDFAS, served as General Chair of ISTFA 2002 and ESREF 2014 and is member of Acatech, the German Academy of Science and Engineering. In recent years, he also investigated CFI techniques as IC hardware security risk.

Invited Talk Topic: Quantitative MIS Characterization Through Electro-Optical Signals

Metal-Insulator-Semiconductor (MIS) systems are the gate structures of FET devices. The characterization uses capacitance-voltages (C-V) curves for identification of flatband and threshold voltages. This presentation discusses how the MIS properties can be transferred into a charge model. The characterization curves of charge over voltage can be contactlessly detected by electro-optical techniques (EOFM, EOP, LVI, LVP). The expected curves will be derived and compared to initial EOFM measurements of FEOL and BEOL test structures.

David Su

David Su was Director of the Failure Analysis Division of TSMC in charge of reliability-related failure analysis, materials and surface analysis including TEM, and chemical analysis from 2000 until 2018. Prior to joining TSMC, he was Director of TEM and FIB Technology Development at Accurel Systems in Sunnyvale, California (1998-2000). From 1991 to 1998 he was TEM Specialist at the Materials Analysis Group of Philips Semiconductors in Sunnyvale, California. He was an adjunct professor at the Department of Materials Engineering at San Jose State University in San Jose, California from 1989 to 1991. David Su received his B.S. degree in Chemical Engineering from the University of Sao Paulo, Brazil and his M.S. and Ph. D. degrees in Chemical Engineering from Stanford University. He has been a board member of the Taiwan Microscopy Society since 2004. He was a board member of the Electronic Device and Failure Analysis Society of the U. S. (2014-2016) and Chair of the Sematech Integrated-Circuit Failure Analysis Council (2013). He was chairman of the 2010 IRPS Failure Analysis Technical Program and was International Chair for ISTFA 2010, 2011 and International Co-Chair in 2013.

Invited Talk Topic: Failure and Materials Analysis in the Logic Integrated Circuit Industry: Status and Challenges in Advanced Nodes

The demands of advanced technology nodes of integrated circuits have pushed failure and materials analysis to their limits. In dynamic fault isolation, improved optical resolution is being constrained by sample preparation. In the materials analysis front, while TEM has very high spatial resolution for imaging, obtaining visual and compositional information, with sub-nanometer resolution, for 3D structures such as fins in FinFET is very challenging. Techniques currently being developed or deployed to address these problems will be discussed including optical and electron beam-based fault isolation, atom probe tomography, He/Ne focused ion beam systems, improvements in FIB and SEM optics and techniques to bring synchrotron-like capabilities to the lab.

Dimitris P. Ioannou

Dimitris Ioannou is a Senior Member of Technical Staff at GlobalFoundries. He received his B.S degree in Physics from the University of Thessaloniki, Greece, and the M.S. and Ph.D. degrees in Electrical Engineering from George Mason University, Fairfax, VA. In 2006, he joined IBM where he played a critical role in the characterization and modeling of reliability mechanisms in advanced Silicon On Insulator (SOI) High-k/Metal Gate CMOS technologies including IBM’s 3D TSV technology. As of 2015 he is with GlobalFoundries where he leads the RF reliability of advanced SOI CMOS and SiGe BiCMOS devices. He has published over 40 papers in the field of CMOS reliability.

Invited Talk Topic: Hot Carrier reliability assessment strategies in advanced RF SOI technologies for 5G applications

Innovations in reliability characterization and modeling of advanced RF Front-End-Modules (FEMs) are critical for maximizing the reliability margins. Emerging reliability issues and the unique challenges associated with components like Low Noise Amplifiers, Switches and Power Amplifiers are highlighted. Possible strategies and techniques are discussed in view of device mission profile and key Figure-of-Merits for each of the FEM’s building blocks.


Francesco Iannuzzo

Francesco Iannuzzo received the M.Sc. degree in Electronic Engineering and the Ph.D. degree in Electronic and Information Engineering from the University of Naples, Italy, in 1997 and 2002, respectively. He is primarily specialized in power device modelling.

He is currently a professor in reliable power electronics at the Aalborg University, Denmark, where he is also part of CORPE, the Center of Reliable Power Electronics. His research interests are in the field of reliability of power devices, including mission-profile based life estimation, condition monitoring, failure modelling and testing up to MW-scale modules under extreme conditions. He is author or co-author of more than 190 publications on journals and international conferences, three book chapters and four patents. Besides publication activity, over the past years he has been invited for several technical seminars about reliability at first conferences as ISPSD, EPE, ECCE, PCIM and APEC.

Prof. Iannuzzo is a senior member of the IEEE (Reliability Society, Power Electronic Society, Industrial Electronic Society and Industry Application Society). He currently serves as Associate Editor for Transactions on Industry Applications, and is secretary elect of IAS Power Electronic Devices and Components Committee. He was the general chair of ESREF 2018, the 29th European Symposium on Reliability of Electron devices, Failure physics and analysis, which scored +400 participants from 43 countries.

Invited Talk Topic: Wear- and Short-Circuit Testing of Silicon Carbide Power MOSFETs

The speech will introduce the present testing techniques for Silicon-Carbide Power Electronic MOSFET, both for wear and short circuit robustness assessment, which are highly demanded for qualification of industrial components. As a major finding, the temperature plays a major role in limiting reliability performance of current-generation devices, and efforts must be devoted in that direction. Modern failure analysis techniques must be used to help in such a process and speed up the learning curve.

Jianfu Zhang

Jianfu Zhang received B.Eng. degree in electrical engineering from Xi’an Jiao Tong University in 1982 and Ph.D. degree from University of Liverpool in 1987. He joined Liverpool John Moores University (LJMU) as a Senior Lecturer in 1992, became a Reader in 1996, and a Professor in 2001.

Dr. Zhang has worked on the qualification of devices and processes for over 30 years, specializing in defects, ageing, modeling, and lifetime prediction of CMOS technologies. He is the author or coauthor of over 200 journal/conference papers, including 55 papers in IEEE Transactions and Electron Device Letters, 19 papers at IEDM/Symposium of VLSI Technology, and 35 invited papers/book chapters. He is/was a member of the technical program committee of several international conferences, including IEDM. His research has been supported by IMEC, ARM, Synopsys, Qualcomm, and the Engineering and Physical Sciences Research Council of UK.

Invited Talk Topic: Challenge and solution for characterizing NBTI-generated defects in nanoscale devices 

Negative bias temperature instability (NBTI) is a well known ageing process for CMOS technologies. Many early works were focused on large devices where device-to-device variations (DDV) are negligible. As device sizes downscale to nanometers, DDV becomes substantial. NBTI is a stochastic process and causes a time-dependent DDV. Characterizing the NBTI-generated defects in nanoscale devices has two main challenges. First, current fluctuates with time and this introduces uncertainties in  measurements. Second, the test time is long and costly: to characterize the NBTI-induced DDV, it is essential to repeat the same test on multiple devices. This work reviews recent progresses in addressing these issues. Based on the As-grown-Generation (AG) model, it will be shown that the measurement uncertainties are dominated by As-grown hole traps and can be removed by subtracting the average value. To reduce the test time, the voltage step stress (VSS) technique is combined with the Stress-Discharge-Recharge (SDR) method. This VSS-SDR technique reduces test time to within one hour per device. The model extracted by VSS-SDR is verified by comparing its prediction with the test data obtained under conventional constant voltage stress.

Kosuke Nagashio

Kosuke Nagashio received the B.E. degree in Materials Science & Engineering from Kyoto University in 1997 and the M.E. and Ph.D. degrees in Materials Engineering from The University of Tokyo in 1999 and 2002, respectively. From 2002 to 2003, he was a postdoctoral research fellow at Stanford University, California. He is currently an Associate Professor with the Department of Materials Engineering, The University of Tokyo. His research interests presently focus on the synthesis, characterization and electron device application of 2D materials. Dr. Nagashio is a member of the Japan Society of Applied Physics (JSAP), the Materials Research Society (MRS), the IEEE Electron Device Society (EDS) and the American Physics Society (APS).

Invited Talk Topic: Reliability of h-BN and its application to 2D heterostructure FET

h-BN has been widely utilized as the substrate and gate insulator to achieve high carrier mobility in graphene and 2D layered channel materials. However, the reliability issue of h-BN itself had not been focused on, since the 2D heterostructure FET had been investigated mainly by the physics researchers. Therefore, we started to study the reliability of h-BN as well as 2D heterostructure FET from the viewpoint of device performance to reveal whether the dielectric breakdowns of 2D layered insulators follow the general breakdown phenomena for 3D amorphous oxides. In this talk, the anisotropic dielectric breakdown of h-BN, heterostructure fabrication by dry transfer technique and performance of 2D heterostructure FET are presented. The perspective on the 2D FET application will be discussed.

Lihong Cao

Lihong Cao is a Director in ASE Group responsible for new packaging technology development (2.5D/3D, FOWLP, FOCoS, PoP, SIP, SESUB), technology promotion, new product introduction, technical program management, strategic planning, and business engagement. Her focusing spans from design, process qualification, root cause analysis and production enablement in HPC (High Performance Computing), AI/MI (Artificial & Machine Intelligence) and 5G/mmWave.

Prior to joining ASE, as a Sr. Manager in AMD, she led global package analysis operations to support product development, qualification, production and customer issues for 28/16/14/7nm technology. She was also in charge of failure analysis technique development and roadmap for advanced package analysis. She not only has semiconductor industries experience, but also had academic and professional experience in National Research Institute and Universities.

Lihong received her Doctoral degree in Material Science & Engineering in Wuhan University of Technology and Research Associate Professor in Nanyang Technology University in Singapore. She has published more than 80 technical papers and held several US patents. She has been a Technical Chair and Tutor in ISTFA since 2011. She was invited as panel member in ISTFA 2018.

Invited Talk Topic: Challenge for Advanced Package Level Fault Isolation

Complex package application in semiconductor process development requires early feedback on systematic and package level defect-driven detractors. The capabilities of current commonly used for non-destructive analysis tools, such as RTX, SAM, TDR and Thermal Imaging, on advanced packaging for 2.5D/3D, FOWLP, PoP have already been exceeded. It is critical to identify current gaps and forecast expected gaps in the package failure analysis in order to provide solutions. New development for the non-destructive fault isolation techniques are discussed on 3D RTX, EOTPR and Thermal Lock-In. The challenge and future development for these techniques are also addressed.