Invited Papers


Mario Lanza

Mario Lanza is a Full Professor at Soochow University since September 2013. Dr. Lanza got his PhD in Electronics in 2010 at Universitat Autonoma de Barcelona. During the PhD he was a visiting scholar at The University of Manchester (UK) and Infineon Technologies (Germany). In 2010-2011 he did a postdoc at Peking University, and in 2012-2013 he was a Marie Curie fellow at Stanford University. Dr. Lanza has published over 100 research papers, including Science, Nature Electronics and IEDM, edited an entire book for Wiley-VCH, and registered four patents (one of them granted with 5.6 Million CNY). He is member of the advisory board of several journals, including Advanced Electronic Materials (Wiley-VCH, Germany), Scientific Reports (Nature Publishing Group, UK), and Nanotechnology (Institute of Physics, UK), and guest editor of an special issue in Advanced Functional Materials (Wiley-VCH, Germany). He is an active member of the technical committee of several world-class international conferences (including IEEE-IEDM, IEEE-IRPS and IEEE-IPFA). Prof. Lanza has received the 2017 Young Investigator Award from Microelectronic Engineering (Elsevier), and the 2015 Young 1000 Talent award (among others), and in 2019 he was appointed as Distinguished Lecturer of the Electron Devices Society (IEEE-EDS). Currently he is leading a research group formed by 15-20 PhD students and postdocs, and together they investigate on the improvement of electronic devices using 2D materials, with special emphasis on two-dimensional (layered) dielectrics and memristors for non-volatile digital information storage and artificial intelligence computing systems.

Invited Talk Topic: Erroneous fabrication and reliability characterization of memristors: how to detect it?

Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different types of computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. In this presentation we describe the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology, and to help researchers to detect those works that (intentionally or unintentionally) show the data in a tricky manner to exaggerate performances and hide weaknesses.

Mu-Chun Wang

Mu-Chun Wang got his Ph.D. in Electrical Engineering from Texas A&M University in 1995. He has ever been a senior device manager at UMC/ Taiwan from 1997 to 2001. He is a full professor of Electronic Engineering at Minghsin University of Science and Technology. He has already published over 436 journal and conference peer-reviewed papers, awarded over 52 USA or Taiwan patents in semiconductor and sensor fields and edited two professional textbooks related to TFT display and nano-node CMOS process in Chinese. He served as 41 journal reviewers including 32 SCI journals and 20 TPC in international conferences as well as being the guest editors in 3 SCI journals plus one technical journal. He was invited as a member of Reviewer Board of Sensors in 2018 and nominated as the Best Reviewers of MEAMT in 2017, 2018 and 2019. More than 160 have been with a professional course lecturer, containing in TSMC, UMC, PowerChip, Winbond, VIS, and JHICC, etc.

Invited Talk Topic: Punch-through and DIBL Effects Exposing Nano-node SOI FinFETs under Heat Stress

Through the electrical measurement plus the heat stress to enhance the existed or latent defects of FinFETs in the nano-node process flow is a useful metrology. This method not only effectively and timely provides the mapping analysis in a whole wafer, but the sensed data may be correlated to the process variation and optimization in statistical analysis. Besides the common electrical characteristics in ON/OFF current, the punch-through and drain-induced barrier lowering (DIBL) effects are good tools to probe the channel integrity. More process parameters related to these two effects are announced.


Sun Litao

Litao Sun is Changjiang Distinguished Professor and serves as the head of School of Electronic Science and Engineering, Southeast University (SEU). He received his PhD from the Shanghai Institute of Applied Physics, Chinese Academy of Sciences in 2005. He worked as a research fellow at the University of Mainz, Germany from 2005 to 2008, and a visiting professor at the University of Strasbourg, France from 2009 to 2010. Since 2008, he joined SEU and honored as a Distinguished Professor. Currently, his research interests focus on: (1) in-situ device microscopy; (2) novel behaviors/properties from sub-10nm materials; (3) applications of nanomaterials in environment, renewable energy and micro/nanosystems. He has published more than 200 peer-reviewed papers including 2 in Science, 13 in Nature and Nature series journals, etc. He holds around 90 patents and has given more than 160 invited presentations. He is the founding chairman of IEEE Nanotechnology Council Nanjing Chapter, the Review Panel member of Graphene Flagship (EU). He has obtained the National Science Fund for Distinguished Young Scholars, Young Leading Talent in Science and Technology Innovation, etc.

Invited Talk Topic: In-situ Device Microscopy

With the development of in situ techniques inside transmission electron microscope (TEM), external fields and probes can be applied to individual nanostrucutures, which extends the capability of TEM and may give new insights into the relationship between atomic structure and unique properties of the materials and related devices. Here we review our recent progress in atomic resolution nanofabrication and dynamic characterization of individual nanostructures and nanodevices based on the idea of “setting up a nanolab inside a TEM”. Additional probes from a special-designed holder provide the possibility to further manipulate and measure the electrical/mechanical/photoelectric properties of the nanostructures in a TEM.

Venkat Ravikumar

Venkat Ravikumar received his Master of Science (Microelectronics) from National University of Singapore in 2007 and has been employed as a Senior member of Technical Staff at Advanced Micro Devices Singapore where he has spent the last 13 years performing Electrical Fault Isolation and Failure Analysis on processors built with the cutting-edge technology node. He mentors research and development efforts for Fault isolation and is responsible for tool, technique enhancements and technology readiness. He is additionally a final year candidate for the Doctorate in Philosophy at the Singapore University of Technology and Design researching on electro-optic effects in transistors. He has received several best paper awards at failure analysis conferences including the most recent best student paper award at ISTFA 2018.

Invited Talk Topic: Challenges in laser probing at spatial resolution compromised technology nodes

Laser probing using NIR lasers at sub-20nm technology has become increasingly difficult due to interaction of the optic probe with multiple transistors. Laser probing waveform is the cumulation of modulations from every active transistor within the optic probe. When multiple transistors are active, they result in “crosstalk” or waveform convolution, resulting in misleading results. In this work, we address some of the typical manifestations of crosstalk and corresponding mitigation strategies for successful probing at resolution compromised technology nodes.

Wu Xing

Dr. Xing Wu received her bachelor’s degree in Electronic Engineering from Xi’an Jiaotong University (XJTU) China in 2008 and her PhD degree from Nanyang Technological University (NTU) Singapore in 2012 (supervisor: Prof. Kinleong Pey). Then, she worked at the Singapore University of Design and Technology (SUTD) and Southeast University (SEU). She is currently a professor at East China Normal University (ECNU) China. She has published more than 90 SCI journal papers including Nature Communications, Advanced Materials, Small, and Applied Physics Letters with more than 2000 citations. She holds more than 20 patents.

Invited Talk Topic: in situ TEM study on flexible electronics reliability and FA

Transmission electron microscopy (TEM), with its high spatial resolution and versatile external fields, is undoubtedly a powerful tool for the static characterization and dynamic manipulation of nanomaterials and nanodevices at the atomic scale. The rapid development of thin-film and precision microelectromechanical systems (MEMS) techniques allows flexile electronics to be probed and engineered inside TEM under external stimuli such as electrical and mechanical, fields at the nanoscale. Here, taking advantage of advanced in situ transmission electron microscopy, we manipulated interfaces of nanomaterials-based flexible pressure sensors. The progress of the in situ TEM paves the way to future wearable devices.

Xing Zhou

Xing Zhou obtained his B.E. degree in electrical engineering from Tsinghua University in 1983, M.S. and Ph.D. degrees in electrical engineering from the University of Rochester in 1987 and 1990, respectively.  He has been with the School of Electrical and Electronic Engineering, Nanyang Technological University, Singapore since 1992.  His past research interests include Monte Carlo simulation of photocarrier transport and ultrafast phenomena as well as mixed-mode circuit simulation and CAD tool development.  His recent research mainly focuses on nanoscale CMOS compact model development.  His research group has been developing a unified core model for nanoscale bulk, SOI, double-gate, nanowire CMOS, as well as III-V HEMTs.  He has given more than 140 IEEE EDS distinguished lectures and invited talks at various universities as well as industry and research institutions.  He is the founding chair for the Workshop on Compact Modeling (WCM) in association with the NSTI Nanotechnology Conference since 2002.  Dr. Zhou was an editor for the IEEE Electron Device Letters (2007–2016), a guest Editor-in-Chief for the special issue of the IEEE Transactions on Electron Devices (Feb. 2014) on compact modeling of emerging devices, and a member of the Modeling & Simulation subcommittee for IEDM (2016, 2017).  He was an Elected Member-at-Large of EDS Board of Governors (2004–2009; 2011–2016) and served as Vice-President for Regions/Chapters (2013–2015). He has been an EDS distinguished lecturer since 2000.

Invited Talk Topic: Reduction of Current Collapse in GaN (MIS)-HEMTs Using Dual Material Gate 

GaN high electron-mobility transistors suffer from various defects or trap states present either in AlGaN barrier or GaN buffer layer. This work presents a different approach to reducing the current-collapse effects in GaN-based transistors by using a dual material gate technology, whereby two different materials having different work functions are merged together to form a single gate, resulting in an improvement of current collapse of around 50%. The current transport efficiency also improves, thus offering improved transconductance. The presence of two gate materials of different work-function modifies the peak electric-field at the drain end, reducing current-collapse and dynamic-Rds,ON degradation.

You Li

You Li received his B.S. degree from the University of Electronic Science and Technology of China, Chengdu, China, in 2003 and M.S. and Ph.D. degrees from the University of Central Florida, Orlando, FL in 2007 and 2010, respectively; all in the electrical engineering. His Ph.D. research work focused on the design of low-capacitance and high-speed Electrostatic Discharge (ESD) devices for low-voltage protection applications. From 2010 to 2012, he worked at Infineon Technologies North America as an application engineer responsible for the system-level ESD protection products. In 2012, he joined IBM as an advisory engineer in the semiconductor research and development center (SRDC), where he worked on the ESD device and model development in 22nm and 14nm Silicon-on-Insulator (SOI) technologies. He has joined GlobalFoundries since 2015 and currently he is leading on ESD devices development in several leading-edge CMOS Bulk and SOI technologies. He is the technical program committee member of EOS/ESD symposium and ESD working group chair of Si2 Compact Model Coalition. He has published over 20 journal and conference papers and granted ~20 patents in ESD area.

Invited Talk Topic: ESD Design and Optimization in Advanced SOI and Bulk FinFET Technologies

As advanced CMOS technologies progress from 2-D planar devices to vertical structures such as the three-dimensional FinFET transistors, the achievement of robust on-chip ESD protection design is challenged by the shrinking of ESD design window since the I/O devices fail at lower breakdown voltage and the reduced ESD performance per footprint due to the significant loss of silicon volume. Similar sized ESD elements employed in SOI technology have even lower ESD performance than Bulk counterparts due to the use of thin silicon film and the presence of buried oxide isolation. In this talk, the design and optimization of several ESD devices including ESD diode, Silicon-controlled Rectifier (SCR) and lateral bipolar will be presented in various SOI and bulk FinFET technologies. The key design parameters and engineering approaches are investigated for ESD performance improvement. The efforts of device design and optimization assure the achievement to ESD design target in the advanced FinFET technologies.

You Wang

You Wang is a research scientist at the School of Microelectronics, Beihang University. He received B.S. degree in optoelectronics from Huazhong University of Science and Technology, Wuhan, China, in 2011, the engineer diploma and M.S. degree in electrical engineering from University of Paris-Sud, France, in 2013, and the PhD degree in electrical engineering from Institut Mines-Télécom, Télécom Paristech, France, in 2017. He is currently working with the research project of design and development of novel circuits based on fault tolerance analysis of spintronic devices. His research interests include spintronic devices modeling, circuit reliability-aware design and novel circuit designs for low power computing methods and security applications. He has authored/coauthored more than 30 scientific papers and was the recipient of ESREF 2014 best poster award.

Invited Talk Topic: Reliability Issues of STT-MRAM and Their Impact on the Performance

Spin transfer torque magnetic random-access memory (STT-MRAM) is considered as a promising candidate for the next generation of memory and computing applications, which may possibly replace SRAM in the future CPU. However, limited to the technology imperfections, STT-MRAM with nanoscale size suffers from considerable reliability issues. This talk will classify the possible reliability issues of STT-MRAM and the current research including theory, experiments and simulations will be presented. Meanwhile, the effects on the performance in terms of access speed, power consumption, area occupancy, PVT robustness, endurance and data retention will be analyzed. Moreover, some possible applications profiting from the intrinsic properties of STT-MRAM will be explored.

Yury Illarionov

Yury Illarionov was born in Leningrad (now St.-Petersburg, Russia) in 1988. He received the B.Sc. and M.Sc. degrees from St.-Petersburg State Polytechnical University in 2009 and 2011, respectively. In 2010 he was awarded with Erasmus Mundus scholarship and in 2012 received the double M.Sc. degree from Grenoble INP and the University of Augsburg within the FAME Master program. In 2015 he received the Ph.D. degree from Ioffe Physical-Technical Institute and Dr.techn. degree from TU Wien. Currently Dr. Yury Illarionov is a postdoc at the TU Wien. He is also a research staff member of Ioffe Physical-Technical Institute. The research interests of Dr. Yury Illarionov are centered around FETs with 2D materials and their reliability and scalability. His most recent achievement is demonstration of MoS2 FETs with record-thin 2 nm crystalline CaF2 insulators. Dr. Yury Illarionov has contributed to more than 60 research works, including papers in Nature Electronics, ACS Nano, Advanced Functional Materials, Nano Energy and 2D Materials among others. He is also a member of Mediterranean Institute of Fundamental Physics (MIFP).

Invited Talk Topic: Reliability of 2D Field-Effect Transistors: from First Prototypes to Scalable Devices

The rich and fascinating properties of two-dimensional (2D) materials have recently inspired various intriguing ideas for post-silicon nanoelectronics. One of the most far reaching of them is the possible substitution of Si with 2D materials in modern field-effect transistors (FETs). Ideally, this should suppress short-channel effects and thus extend Moore’s law below 5 nm channel lengths, while maintaining and possibly even overcoming the high performance of commercial Si devices. However, despite recent progress at fabricating 2D FETs, there is still no commercially competitive transistor technology. One of the main reasons for this is the relatively poor reliability of typical 2D FET prototypes, which suffer from hysteresis and bias-temperature instabilities (BTI) of the transistor characteristics. Despite this, the attention paid to this serious problem is impermissibly low. In my talk I will discuss the main achievements at understanding the reliability of various 2D FETs, from the first prototypes to recently reported scalable devices.