Prof. Aaron Thean
Aaron Thean is a Professor of Electrical and Computer Engineering at the National University of Singapore (NUS), since May 2016. His current research interests involve Heterogeneous Integration of Nano-systems and Hybrid-Flexible Electronics. He is the Director of NUS’ new central Nanofabrication Center. Besides his NUS responsibilities, Aaron serves on the Scientific Advisory Board for the NUS-MIT research alliance SMART-LEES, A*Star IME, and Huawei Singapore Research Center. He is currently an Editor of IEEE Electron Device Letters. Prior to his transition to NUS, Aaron was the Vice President of Logic Technologies and the Director of the Logic Devices Research at IMEC. From 2011 to 2016, he directed the research and development of device technologies ranging from ultra-scaled FinFETs to III-V/Ge Channels, emerging nano-device architectures, logic spintronics, and novel materials. Before 2011, Aaron was with Qualcomm’s CDMA technologies in San Diego, California. Before Qualcomm, Aaron was the Device Manager at IBM East Fishkill New York, where he led his team to develop the industry’s first gate-first metal-gate 28-nm and 32-nm low-power bulk CMOS technologies. The technology was successfully commercialized by IBM’s foundry partners and enabled some of today’s most successful mobile devices. Aaron started his industry career at Freescale Semiconductor (and Motorola) where he did research on many novel devices that included Strained-Si-On-Silicon, FinFETs, FDSOI, and Nanocrystal Flash Memory. Aaron graduated from University of Illinois at Champaign-Urbana, USA, where he received his B.Sc (Highest Honors), M.Sc, and Ph.D degrees in Electrical Engineering. He has published over 300 technical papers and holds more than 50 US patents. Among his notable recognitions, he and his IMEC team received the 2014 Compound Semiconductor Industry Innovation award for their IIIV FinFET work. Aaron returned to Singapore in 2016 to receive the National Research Foundation (Singapore)’s Returning Singapore Scientist Award and started his career in academia.
Tutorial Topic: FinFET & Post-FinFET Advanced Logic Device Reliability– A Review
Over the last decade, CMOS logic technologies have incorporated several material disruptions. Advanced CMOS made the transition from Poly-SiON to High-k metal gate (HKMG) process about 10 years ago, for 45nm and 32nm/28nm planar CMOS transistors developed from 2007 to 2009, respectively. The efforts to bring these technologies to high-volume manufacturing accelerated our learning on gate-stack reliability, especially the role of thermal budget management on the replacement metal-gate process. There are major influences of gate PBTI and NBTI due to the device integration scheme like dopant activation and silicidation. For example, “high-k-first” and “high-k-last” gate stacks showed different reliability potentials. However, with process and integration schemes, we found solutions to engineer both stacks to meet requirements.
The next disruption came quickly as we transitioned from planar to FinFET technologies in 2011, with Intel’s 22nm CMOS. This coincided with the capabilities of Atomic Layer Deposition (ALD) technologies for the the HKMG process. The lessons learnt on managing BTI impact did carried forward, but we now contend with new influences due to a different dielectric-crystalline interface of the fin sidewalls and the process challenges of a largely vertically oriented gate structure. We saw that ALD material improvements helped us overcome some of the issues. However, with increased current densities and aggressive dimensional scaling, hot-carrier and device self-heating rose to top of the issue list. Following the current success of 14nm/16nm FinFET technologies, we will soon be seeing the 3rd generation FinFET technologies with upcoming10nm and 7nm CMOS, in the coming two years. However, there are still really few knobs to overcome these top issues at the material or process levels. Except, at the circuit design or system levels through engineering the use conditions.
The next disruptions may come at or after 5nm CMOS targeted for 2020. With the need for more performance, new materials like SiGe fins are being considered for integration, or stacked Nanowires. We see exciting new reliability understanding and opportunities brought forth with these new materials and structures. Beyond FinFETs and beyond Si, we will need to prepare for low-thermal budget processes (E.g. for III-V, Ge). Encouragingly in recent years, we have gained significant new insights towards reliable low-thermal budget gate stacks. This will pave the way needed to realize the integration of these new materials for the Fin or Nanowire devices. In this presentation, we will review this evolution of understanding in reliability physics driven by this relentless revolution of device and material architectures to continue Moore’s law.