C. ‘Raman’ Kothandaraman

C. Kothandaraman is a Research Staff Member at IBM Research in Yorktown Heights, NY. He received his B.Tech., degree from Indian Institute of Technology, Madras, India and his PhD from Columbia University, NY, USA. At IBM, he played a critical role in the development and characterization of IBM’s 3D TSV technology. He has published widely on the impact of 3D TSV technology and chaired several technical sessions in this field. His current research interests include 3D integration, non-volatile memories, magnetic materials and devices for advanced CMOS applications. He has published over 50 papers and holds more than one hundred patents relating to advanced CMOS technologies.

Tutorial Topic: Reliability Challenges for 3DIC 

Due to the saturation of performance in advanced CMOS technologies with traditional device scaling, 3D integration has been proposed as a solution to improve power-performance characteristics of advanced CMOS systems. However, the introduction of the Through Silicon Via (TSV), to interconnect the different strata that comprise the 3DIC, has resulted in perturbations to the underlying CMOS devices. This tutorial will review the physics of these perturbations and will cover their impact on the underlying CMOS reliability. Challenges to both the front-end-of-the line device reliability as well as the impact on interconnects will be described. Methodologies to study the reliability of the CMOS chip will be presented and results from their applications will be described.

Dr Lihong Cao

Lihong Cao is a Director in ASE Group responsible for new packaging technology development (2.5D/3D, FOWLP, FOCoS, PoP, SIP, SESUB), technology promotion, new product introduction, technical program management, strategic planning, and business engagement. Her focusing spans from design, process qualification, root cause analysis and production enablement in HPC (High Performance Computing), AI/MI (Artificial & Machine Intelligence) and 5G/mmWave.

Prior to joining ASE, as a Sr. Manager in AMD, she led global package analysis operations to support product development, qualification, production and customer issues for 28/16/14/7nm technology. She was also in charge of failure analysis technique development and roadmap for advanced package analysis. She not only has semiconductor industries experience, but also had academic and professional experience in National Research Institute and Universities.

Lihong received her Doctoral degree in Material Science & Engineering in Wuhan University of Technology and Research Associate Professor in Nanyang Technology University in Singapore. She has published more than 80 technical papers and held several US patents. She has been a Technical Chair and Tutor in ISTFA since 2011. She was invited as panel member in ISTFA 2018.

Tutorial Topic: Advanced 2.5D/3D Package Level Failure Analysis

IC packages are becoming increasingly complex due to the large body size, small form factor and application of integrated packages such as MCM (multi-chip modules), POP (package on package), FOWLP (fanout wafer level package), Chiplets MCP (multi chip package), SIP (system in package) and 2.5D & 3D stacked die package. Package level failure analysis has become very challenging. Efficiently detecting and localizing the failure in order to drive root cause has become very critical. This tutorial will provide a brief overview of the package level failure analysis techniques including electrical verification and advanced fault isolation for 2.5D/3D stacked packages. Given an “alphabet soup” of isolation techniques available, the choice of the optimal technique for a particular fail can be very challenging. The tutorial will also focus on how to make a decision on which techniques are best suited for the defect types commonly occurred in package level, followed by FA examples.

Dr. Baozhen Li

Baozhen Li is a Senior Technical Staff Member (STSM) at IBM Systems. He has been working on technology reliability for more than 20 years.  His experiences cover a wide range of reliability aspects, including electromingttion (EM), stress migration (SM), dielectric breakdown (TDDB), thermal mechanical stability and chip-package interactions (CPI). In addition to reliability studies for leading edge semiconductor technology development, he also works on reliability design optimization and chip level reliability for high end computing systems.  He publishes and patents extensively in the semiconductor technology and reliability area.  He has given multiple tutorials and invited talks at international conferences and wrote multiple invited introductory papers in journals. He received a bachelor’s degree from Northeastern University in China and Ph. D degree from the University of Notre Dame in USA.

Tutorial Topic: MOL & BEOL Reliability Challenges for Advanced Technology Nodes

Aggressive technology scaling places severe challenges on patterning, process integration, material selection and reliability.  In this tutorial, the interactions among these challenges will be highlighted.  The focus will be on middle of line (MOL) and back end of line (BEOL) reliability challenges including electromigration (EM), dielectric integrity (TDDB), and Stress Migration (SM).  After a review of the fundamentals of each reliability mechanisms, details will be given on how the new patterning, integration schemes and material sets impact each of the reliability failure mechanisms.  To meet these challenges, demands and progress on new understanding, innovation and reliability models will also be reviewed

Dr. David Su

David Su was Director of the Failure Analysis Division of TSMC in charge of reliability-related failure analysis, materials and surface analysis including TEM, and chemical analysis from 2000 until 2018. Prior to joining TSMC, he was Director of TEM and FIB Technology Development at Accurel Systems in Sunnyvale, California (1998-2000). From 1991 to 1998 he was TEM Specialist at the Materials Analysis Group of Philips Semiconductors in Sunnyvale, California. He was an adjunct professor at the Department of Materials Engineering at San Jose State University in San Jose, California from 1989 to 1991. David Su received his B.S. degree in Chemical Engineering from the University of Sao Paulo, Brazil and his M.S. and Ph. D. degrees in Chemical Engineering from Stanford University. He has been a board member of the Taiwan Microscopy Society since 2004. He was a board member of the Electronic Device and Failure Analysis Society of the U. S. (2014-2016) and Chair of the Sematech Integrated-Circuit Failure Analysis Council (2013). He was chairman of the 2010 IRPS Failure Analysis Technical Program and was International Chair for ISTFA 2010, 2011 and International Co-Chair in 2013.

Tutorial Topic: Principles and Applications of TEM and FIB in the Semiconductor Industry

The demands of failure and materials analysis for advanced technology nodes of the integrated circuit industry have pushed Transmission Electron Microscopy (TEM) and Focused Ion Beam (FIB) systems to their limits, especially the need to obtain 3D information both visually and compositionally in the nanometer size range. In this tutorial, the principles and applications of these techniques will be discussed. In addition to conventional imaging and elemental analysis, techniques such as strain measurement, tomography will be presented. The important area of sample preparation will be addressed as well as efforts to automate both data acquisition and sample preparation. Finally, advances in FIB circuit editing will also be discussed.

Prof. F. Iannuzzo

Francesco Iannuzzo received the M.Sc. degree in Electronic Engineering and the Ph.D. degree in Electronic and Information Engineering from the University of Naples, Italy, in 1997 and 2002, respectively. He is primarily specialized in power device modelling.

He is currently a professor in reliable power electronics at the Aalborg University, Denmark, where he is also part of CORPE, the Center of Reliable Power Electronics. His research interests are in the field of reliability of power devices, including mission-profile based life estimation, condition monitoring, failure modelling and testing up to MW-scale modules under extreme conditions. He is author or co-author of more than 190 publications on journals and international conferences, three book chapters and four patents. Besides publication activity, over the past years he has been invited for several technical seminars about reliability at first conferences as ISPSD, EPE, ECCE, PCIM and APEC.

Prof. Iannuzzo is a senior member of the IEEE (Reliability Society, Power Electronic Society, Industrial Electronic Society and Industry Application Society). He currently serves as Associate Editor for Transactions on Industry Applications, and is secretary elect of IAS Power Electronic Devices and Components Committee. He was the general chair of ESREF 2018, the 29th European Symposium on Reliability of Electron devices, Failure physics and analysis, which scored +400 participants from 43 countries.

Tutorial Topic: Testing for Reliability of Power Electronic Components

The tutorial introduces the modern principles of testing for reliability of power electronic components. After a short introduction about CORPE – the center of Reliable Power Electronics at Aalborg University, where expectations from power electronics industries will be presented as well, some reliability theory fundamentals will be given, along with practical details about common testing protocols. Wear/life testing types will be then presented and classified, each with its specific aim. The last part will be about the original test approach at Aalborg University, both for Silicon IGBTs and Silicon Carbide MOSFETs, which are by far the most used components in medium-voltage power electronics. Some prospects about failure analysis will conclude the tutorial.

The expected audience includes students and industry engineers who want to get basic-intermediate information about reliability theory and modern challenges.

Prof. Jian Fu Zhang

Jian Fu Zhang received B.Eng. degree in electrical engineering from Xi’an Jiao Tong University in 1982 and Ph.D. degree from University of Liverpool in 1987. He joined Liverpool John Moores University (LJMU) as a Senior Lecturer in 1992, became a Reader in 1996, and a Professor in 2001.

Dr Zhang has worked on the qualification of devices and processes for over 30 years, specializing in defects, ageing, modeling, and lifetime prediction of CMOS technologies. He is the author or coauthor of over 200 journal/conference papers, including 55 papers in IEEE Transactions and Electron Device Letters, 19 papers at IEDM/Symposium of VLSI Technology, and 35 invited papers/book chapters. He is/was a member of the technical program committee of several international conferences, including IEDM. His research has been supported by IMEC, ARM, Synopsys, Qualcomm, and the Engineering and Physical Sciences Research Council of UK.

Tutorial Topic: BTI: Testing and Predictive Modelling

Bias temperature instabilities (BTI) of MOSFETs are well known ageing processes and their qualification is essential for CMOS technologies. To modelling BTI and qualify device lifetime, the common practice is to extract BTI model based on accelerated ageing tests. Several models were proposed by early works and their ability to fit the test data is often demonstrated. This tutorial will show that some models cannot accurately predict the BTI under use-conditions, where ageing is slow. The As-grown-Generation (AG) model is introduced and its predictive capability is demonstrated. The key for the success of AG model is an accurate separation of defects into as-grown defects and generated defects. After presenting a defect framework and the evidences for it, this tutorial will describe the detailed techniques for the defect separation and a step-by-step guide for their implementation. It will be shown that different defects have different ageing kinetics and how the correct time exponent can be extracted independent of test conditions. AC modelling and defect discharging also will be addressed. The connection and difference between AG model and the JEDEC procedure will be clarified.

Szu Huat, Goh

Szu Huat received his BEng and PhD in electrical and computer engineering from the National University of Singapore. He is currently with GLOBALFOUNDRIES, where he leads a team responsible for product failure diagnostics and advanced methodologies to accelerate yield ramp. He focuses on the development of wafer-level dynamic fault isolation techniques combining with cross-functional domain knowledge of software, design and test to enhance yield learning. His current exploration centers on machine learning to enhance FA and yield prediction. He is the technical program chair, general co-chair and general chair for the International Physical and Failure Analysis (IPFA) in 2016, 2017 and 2018

Tutorial Topic: Advanced Fault Isolation Technologies: Design House and Foundry Perspectives

Fault isolation plays a critical role in the overall failure analysis process. Although the eventual objective as one of the initial steps to narrow the failure search area is similar, in fact, there are significant differences in the conduct of fault isolation between design houses and foundries, especially, in advanced applications. Instead of an over-emphasis on the generic descriptions of tools and techniques, this tutorial approaches the topic from different perspectives to present a holistic view on fault isolation. Challenges, future roadmaps and emerging applications will also be discussed.


  1. Introduction to the role of fault isolation
    1. Failure analysis workflow
    2. Failure debug and yield engineering
    3.  Overview of fault isolation techniques (software, hardware, static, dynamic, global, local)
  2. Equipment Setup and Workflows
    1. Software-based techniques setup workflow and challenges
    2. Motivation for dynamic fault isolation approaches
    3. Hardware-based techniques setup workflow and challenges
      1. Hard-dock, soft-dock
      2. Wafer, package
      3. Challenges: cooling, optical resolution, vibration etc.
    4. Introduction to test fundamentals
      1. Typical test flow, terminologies, common debug tools
  3. Global Dynamic Fault Isolation techniques: Concepts/ Principles and Applications
    1. Emission-based (PEM, Thermal, Spectroscopy)
    2. Laser-based (SDL, LADA, TRLADA, FM/LVI, 2nd harmonic, phase mapping, 2pLADA, EeLADA)
  4. Local Dynamic Fault Isolation techniques: Concepts/ principles and Applications
    1. Laser-based (LVP)
    2. Nanoprobing
  5. Other Emerging Techniques

Venkat Ravikumar

Venkat Ravikumar received his Master of Science (Microelectronics) from National University of Singapore in 2007 and has been employed as a Senior member of Technical Staff at Advanced Micro Devices Singapore where he has spent the last 13 years performing Electrical Fault Isolation and Failure Analysis on processors built with the cutting-edge technology node. He is additionally a final year candidate for the Doctorate in Philosophy at the Singapore University of Technology and Design researching on electro-optic effects in transistors.