C. ‘Raman’ Kothandaraman
C. Kothandaraman is a Research Staff Member at IBM Research in Yorktown Heights, NY. He received his B.Tech., degree from Indian Institute of Technology, Madras, India and his PhD from Columbia University, NY, USA. At IBM, he played a critical role in the development and characterization of IBM’s 3D TSV technology. He has published widely on the impact of 3D TSV technology and chaired several technical sessions in this field. His current research interests include 3D integration, non-volatile memories, magnetic materials and devices for advanced CMOS applications. He has published over 50 papers and holds more than one hundred patents relating to advanced CMOS technologies.
Tutorial Topic: Reliability Challenges for 3DIC
Due to the saturation of performance in advanced CMOS technologies with traditional device scaling, 3D integration has been proposed as a solution to improve power-performance characteristics of advanced CMOS systems. However, the introduction of the Through Silicon Via (TSV), to interconnect the different strata that comprise the 3DIC, has resulted in perturbations to the underlying CMOS devices. This tutorial will review the physics of these perturbations and will cover their impact on the underlying CMOS reliability. Challenges to both the front-end-of-the line device reliability as well as the impact on interconnects will be described. Methodologies to study the reliability of the CMOS chip will be presented and results from their applications will be described.