CALL FOR PAPERS

Be Part of the Conversation

CALL FOR PAPERS

20 – 23 JULY 2020

MARINA BAY SANDS

SINGAPORE

 

IEEE 27th INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS

 

IPFA 2020 is devoted to the fundamental understanding of the electrical and physical characterization techniques and associated technologies that assist in probing the nature of wear-out and failure in conventional and new CMOS devices, in turn resulting in improved knowhow of the physics of device / circuit / module failure that serves as critical input for future design for reliability. The Technical Program Committee is inviting papers related, but not limited to, the following areas:

(Special Session) Emerging Topics in Failure Analysis and Reliability: New FA Techniques, FA for hardware security, Artificial intelligence (AI) for FA – fault detection, visual / image analytics, pattern recognition.

Sample Preparation, Metrology and Defect Characterization: Device deprocessing; Ion beam / TEM sample preparation, Metrology, Defect inspection, Test chips.

Case Studies on Fault Isolation: Die / Board / System-level electrical FA, Electrical characterization and nanoprobing.

Case Studies on Physical Failure Analysis: Die / Board / System-level physical FA, Design for manufacturing, Construction Analysis, Reverse engineering.

Package-Level Failure Analysis: 2.xD / 3D Package FA, Magnetic/acoustic applications, 2.x D/ 3D X-ray,  lock-in thermography, FTIR, non-destructive failure analysis, Workflows.

Advanced Electrical Fault Isolation Techniques: Advanced methodologies in photon and laser-based microscopy techniques, Dynamic techniques, Acoustic microscopy, Magnetic imaging, Nanoprobing, AFP, EBAC/EBIC.

Advanced Physical Failure Analysis Techniques: Advanced methodologies in PFA, Advanced optical beam, Ion beam approaches, Circuit-edits, Delayering recipes and innovations. Tomography.

(New!) Product Test and Diagnostic: Embedded BIST and DFT test and diagnosis, Reliability testing, Silicon failure debug on test and yield engineering methodologies.

Transistor and NVM Reliability: Gate oxide/High-κ Reliability, PBTI/NBTI, Hot carrier, Random Telegraph Noise and single dopant effects, Self Heating in Sub-10 nm CMOS. Process and stress-induced reliability issues and variability, Non-volatile memory reliability – retention, endurance and read disturb in PCRAM, RRAM, STT-MRAM, reliability of ferroelectric devices.

ESD, Latchup and Reliability for Space Applications: Component and system level ESD design : modeling and simulation, Neutron and alpha particle single event radiation, multi-bit SER/SEU.

Interconnect and Packaging Reliability: TDDB dielectrics, Electromigration, stress migration, cracking, corrosion, and fatigue in bond pads, reliability of 3DIC and TSV, Thermo-mechanical stress, power dissipation issues, wafer warpage, wire bonding, die attach and encapsulation issues, wafer bonding technology, yield and reliability.

(New!) Photonics Device (Display, lighting and Photovoltaic) Reliability and Failure Analysis: Display modules, LED, solar cells made of silicon, CdTe, CIGS, organic materials, multi-junction, perovskite etc., infrared photodetectors, waveguides.

High Power Electronics / Wide Bandgap Device Reliability & Failure Analysis: Reliability of devices based on GaAs, GaN, SiC and Ga2O3  systems, Trap-related degradation;  materials-related defect characterization, process variability, III-V/Si integration.

2D Materials and Devices: Reliability & Failure Analysis: Tunnel FETs, transistors with 2D materials (Graphene, MoS2, WSe2, h-BN), ferroelectric and negative capacitance FETs, quantum computing, spintronics.

SUBMISSION GUIDELINES

Prospective authors are requested to submit at least a two-page abstract (including text and figures) of their previously unpublished and original research work. The two-page abstract should include the following:

  1. Brief introduction to the background and motivation/objectives of the work.
  2. Experimental results, analysis and discussion.
  3. Summary of the findings, highlighting their impact, novelty and importance.
  4. Supporting figures, tables, and references.

All submissions must be in English. The materials in the paper must be original and unpublished. Please work on the abstract according to the provided template in the IPFA webpage. Only electronic submissions in PDF format will be accepted.

Please limit your submission file size to 5 MB and submit your abstract through the IPFA Website https://www.ipfa-ieee.org/2020 by 8 February 2020. For further details please contact the Technical Program Chair / Co-Chair (details provided below).

Authors of papers that have been accepted for oral / poster presentation will be notified by 14 March 2020. Upon notification of acceptance, authors will be asked to submit a final manuscript (mandatory and to be submitted by 30 May 2020). High quality papers presented at IPFA 2020 will be invited to submit an extended version of their work for the Special Issue of Microelectronics Reliability journal (Elsevier), expected to be published in DEC 2020.

IMPORTANT DATES

1 December – 8 February 2020              Submission of Abstract

14 March 2020                                          Notification of Abstract Acceptance

30 May 2020                                              Final Manuscript Submission Due

 

Conference Chairman                                           

Nagarajan Raghavan

SUTD, Singapore

nagarajan@sutd.edu.sg

 

Technical Program Chair

Wardhana Sasangka

SMART, Singapore

wardhana@smart.mit.edu

 

Technical Program Co-Chair

Alfred Quah

GLOBALFOUNDRIES Singapore

alfred.quah@globalfoundries.com