Invited Speakers

Speakers

Dr. Alok Ranjan

Dr. Alok Ranjan is currently a postdoctoral research fellow at Engineering Product Development (EPD) pillar at Singapore University of Technology and Design (SUTD). Alok’s current research interest includes development of physical and failure analysis techniques for emerging nanoscale devices. Alok has obtained his PhD in the field of nanoscale reliability of gate dielectrics under Prof. Pey Kin Leong (SUTD) and Dr. Sean O’Shea (IMRE, A*STAR). During his PhD, Alok has been extensively applying the scanning probe microscopy techniques under UHV for the isolation of individual defects and its electrical characterization using random telegraph noise spectroscopy techniques. Alok has published more than 20 technical papers (journals and conference proceedings) and a book chapter, including 5+ technical papers presented as a lead author at International Reliability Physics Symposium (IRPS) – being one of the top tier conferences in the field. Alok also sits on the reviewer panel for various journals including Applied Physics Letters, Scientific Reports, ACS Applied Materials and Interfaces, Microelectronics Reliability and conferences including International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA). Alok has also won numerous awards including academic gold medal (Bachelors) and graduate research competition awards from applied materials.

Invited Talk Topic: Advances in Applications of Conduction AFM Techniques for Gate Oxide Reliability Analysis at Nanoscale

Conduction AFM (CAFM) is used to measure localized electrical properties of a surface or nanoscale device. What is less appreciated is the interplay between the electrical and mechanical behavior. I will present few examples involving friction and adhesion from our work studying the dielectric breakdown of ultrathin films in ultra-high vacuum. In the first case, I will describe an experimental approach to quantify thermal drift in nanoscale conduction measurements and also discuss an approach to prolong the dwell time of the CAFM tip at a location needed for time dependent spectroscopy. In the second case, I will describe a new method that correlates changes in the adhesion and the electrical stress induced defects in dielectric thin films. Taking a simple case of SiO2, we demonstrate that adhesion at the CAFM tip-oxide contact increases after electrical stress primarily due to interplay between chemical / ionic bonding as well as electrostatic interactions between stress induced defects and the CAFM tip. This new approach has potential to infer the trapped charge densities at the nanometer length scales in dielectrics.

Dr. Andrew Kim

Andrew Kim is a senior staff at CMOS reliability R/D team of NSG (Non-volatile memory Solutions Group), Intel Corporation, Folsom, CA, USA. His current focus is BEOL reliability of Cu interconnects. He served as a chair/vice-chair of Dielectric Committee of IRPS2019/2018. Since 1998, he has been working on semiconductor interconnect reliability, BEOL process integration, eFuse design/reliability, TCAD on strained silicon, CMP modeling at various companies (IBM, Samsung and Texas Instruments), gas turbine design and system reliability team at General Electric. He received a B.S. with a minor in Mathematics in 1995 from California State University, Fullerton, CA, M.S. and Ph.D., respectively in 1996 and 2001, from Rensselaer Polytechnic Institute, Troy, NY, all in Mechanical Engineering.

Invited Talk Topic: Challenges of XEOL (X=F, M and B) Time-Dependent Dielectric Breakdown Reliability in advanced CMOS technologies 

Time-dependent dielectric breakdown reliability has always been one of the major reliability concerns in advanced CMOS technologies across FEOL (Front-End-of-Line), MOL (Middle-End-of-Line) and BEOL (Back-End-of-Line). TDDB has become even more challenging and it is only expected to become more complex in current and future technology nodes by new integration schemes and new materials in all FEOL, MOL and BEOL. In this talk, focused reviews will be presented on TDDB evaluation challenges, available voltage acceleration models, statistical models to consider dielectric thickness variation effect on TDDB time-to-fail and fast screening methods (Ramped Voltage Stress and Ramped Current Stress) applicable to FEOL, MOL and BEOL dielectrics.

Dr. Franco Stellari

Franco Stellari (S’95–M’04-SM’06) received the M.S. degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 1998 and 2002 respectively. He subsequently joined the IBM T.J. Watson Research Center in Yorktown Heights, NY as a post-doc, becoming a permanent Research Staff Member in 2004. His major interest is the development and use of new optical techniques for testing VLSI circuits based on static imaging, time resolved emission and laser based techniques. During the years he has worked with single-photon detectors with fast response time and very high quantum efficiency, such as InGaAs Single Photon Avalanche Diodes (SPADs) and Superconducting Single Photon Detectors (SSPD), pushing their limits towards record low voltage applications. In 1999 he developed a model of the transistor emission that is still currently used for estimating luminescence from electric circuits. He has also developed a novel methodology for studying latch-up ignition, process variability, power supply noise measurement, and signal integrity. More recently, he has worked on fully exploiting the Light Emission from Off-State Leakage Current (LEOSLC) to developed novel techniques for VLSI circuit testing and hardware security such as chip alterations detection, and logic state mapping, chip reverse engineering, etc. His work leverages the development of automated data collection, advanced analysis, image processing, and computer vision for signal isolation and data extraction. He has more than 100 international publications, more than 45 granted patents. Some of his work in the field of advanced detectors was recognized with the Paul F. Forman Team Engineering Excellence Award in 2015. He was also the recipient of the IEEE EDS Paul Rappaport Award for the best Trans. on Electron Devices of 2004, the Best Poster Award at the International Symposium for Test and Failure Analysis (ISTFA) in 2014, and the Best Paper Award at the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) twice, in 2002 and 2004.

Invited Talk Topic: 1D and 2D Time-Resolved Emission Measurements of Circuits Fabricated in 14 nm Technology Node

TRE measurements for circuit debugging, fault localization, and circuit characterization are discussed along recent detectors developments that have improved their low-voltage sensitivity, while maintaining an excellent jitter and low noise performance. Advantages and disadvantages of TRE methodologies are discussed and contrasted with laser probing techniques. 14 nm test cases are presented for logic debug, SRAM characterization, and early technology development. Finally, several advanced applications that are mostly unique to TRE have been summarized. TRE has a unique capability to contribute to test and diagnostics applications, especially when conditions make laser-based technique difficult to use due to the lack of resolution or invasiveness.

Dr. Frank Huang Weidong

Weidong Huang (Frank) is currently working as a Director of Device Analysis Engineering in Microsoft China leading the Materials and Physical Analysis Team, which support Microsoft Hardware Products. He has 17 years of work experience in electronic device and semiconductor field with specializing in Materials and Physical analysis, as well as Reliability test. He worked as key organizer and Exhibition Chairman of IPFA 2009 in Suzhou, also as Vice Technical Chair of IPFA 2013 in Suzhou. His education background is Solid State Physics and Materials Science, especially in Advanced Applied Materials and Electronic Packaging materials, with Ph. D degree from Chinese Academy of Science.

Invited Talk Topic: Analysis of a Novel Failure Mode for Wide Gamut wLED Back-light Module

It is always a challenge for system supplier to investigate root cause failure analysis on sub-system or component level issues. In this talk the failure analysis on a white LED back-light module in a portable computer device  was studied as an example to compare the different FA mindset and results from system supplier and component supplier. Failure mechanism, FA cooperation work model, root cause and lesson leant also discussed.

Dr. Jong-Shing Bow

Invited Talk Topic: Advanced Circuit-Edit via Focused Ion Beam and its Challenge

The IC function re-check and confirmation are usually relied on the circuit-edit via FIB first, and it really reduces time-to-market during IC development. A circuit-edit via FIB on 7 nm chip is demonstrated, even in back-side process.  We also make failure analysis to observe the failure mode once circuit-edit fail. The challenge of current circuit-edit via FIB on the advanced IC is discussed.

Dr. Umberto Celano

Umberto Celano is a Senior Scientist at imec (Belgium), with expertise in materials analysis for semiconductor technology, device physics and nanoscale functional materials. He received his Ph.D. in Physics from the University of Leuven – KU Leuven (Belgium) in 2015. His research has established a novel three-dimensional nanoscale imaging technique that combines sensing with sub-nm material removal to study materials in confined volumes. Currently, Dr. Celano’s research interests encompass nanoelectronics, nanophotonic, functional materials and VLSI metrology. In these areas, he conducted research in various institutions including KU Leuven, Osaka University and Stanford University.

Umberto is the recipient of the Rogen A. Haken Best Paper Award at IEDM (2013) and has authored or co-authored 60+ papers in international journals and conference proceedings. He is part of the metrology working group for the International Roadmap for Devices and Systems (IRDS) and acted as member of the early carrier editorial board of Nano Letters. Previously, Umberto received his B.Eng. in Electronic Engineering and a M.Sc. degree in Nanoelectronics with honors from the University of Rome Sapienza, Italy.”

Invited Talk Topic: Correlative Metrology for the Analysis of Ferroelectric Doped-HfO2

Ferroelectric (FE) doped-hafnia (HfO2) holds the promise of a lead-free material system to reignite integrated ferroelectrics in microelectronics with impact on fast switching logic devices, low-power and high-density non-volatile memory and integrated sensors. Therefore, it does not surprise the growing interest of both academic and industrial communities. However, evaluating nanometre-scale materials properties to correlate with FE-device operations represents often a challenge due to the intertwined paraelectric and ferroelectrics effects occurring in thin oxides (e.g., leakage current, charge-trapping, and dielectric breakdown). Here, by using different techniques and device structures, we present a combination of electrical characterization and correlative metrology to access multiple material properties in FE-HfO2. This is reported while maintaining the required nanometric spatial resolution and sensitivity for the analysis of variations in surface potential, leakage current and converse piezoelectric effects.

Professor Christian Boit

Prof. Christian Boit retired 2018 from Chair of Semiconductor Devices Department at Technische Universitaet Berlin, Germany. His research focuses on IC failure analysis (FA) and contactless fault isolation (CFI). In recent years, he was also investigating hardware security risks introduced by CFI. Chris started at Siemens Semiconductors 1986 and participated 1990 -1993 in IBM / Siemens DRAM project East Fishkill, NY. Later, he was Director of FA at Infineon Technologies until taking the university position in 2002. Chris is an active supporter of the FA community. He was co-founder of EDFAS and General Chair of ISTFA 2002 and ESREF 2014.

Invited Talk Topic: TBC

Professor Tan Chuan Seng

Professor Chuan Seng Tan received his BEng degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his MEng degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure) and in September 2019, he was promoted to the rank of full professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He provides his service as committee member for International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, IEEE-EDTM, IEEE-GFP and ECS-Wafer Bonding. He is an associate editor for Elsevier Microelectronics Journal (MEJ) and IEEE Transactions on Components, Packaging and Manufacturing Technology. He is a senior member of IEEE and a recipient of the 2019 Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS). Beginning in June 2019, he serves as a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019.

Invited Talk Topic: 3D MIM Capacitor Embedded in TSV: A novel on-chip integrated capacitor

In this work, a novel integrated capacitor, called “3D MIM Capacitor Embedded in TSV” is proposed, designed, fabricated, and characterized for application in integrated circuits (ICs) with through-silicon vias (TSVs). A significant capacitance density enhancement can be achieved for this 3D embedded capacitor, because it leverages on the high aspect ratio structure of TSVs. Compared to conventional trench capacitor, this technology does not consume additional silicon area because it is embedded in the trenches of existing TSVs, instead of dedicated trenches. An ultrahigh capacitance density of 5,621.8 nF/mm2 was envisioned according to our model, which is ~13× of 440.0 nF/mm2 from a conventional trench capacitor with the same design parameters. A leakage current density as low as 1.61×10-7 A/cm2 at 4.3V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3,776.6 nF/mm2. In addition, the reliability of the 3D MIM and potential new applications it enables are discussed.

Professor Weidong Zhang

Weidong Zhang is a professor of nano-electronics, leading the memory devices research at Liverpool John Moores University (LJMU), where the research in this field is ranked 11th and 26th in the last two UK government research assessments. He is the principal investigator and co-investigator of a number of research projects with a total value of more than £3 million, including five prestigious research grants from the Engineering and Physical Sciences Research Council (EPSRC), a leading UK government research funding council. He has led the LJMU’s collaboration with IMEC memory device group for the past 14 years, whose partners include Intel, Micron, Samsung, western Digital, SK Hynix and Toshiba. His current research interests include characterization and quality assessment of resistive switching and flash memory and selector devices, CMOS devices based on Si, Ge and III-V materials, and GaN HEMT devices. His work is predominantly published in international journals and premier conferences, including Applied Physics Letters, IEEE Electron Device Letters, IEEE Transactions on Electron Devices. He has co-authored 10 papers in the flagship IEEE International Electron Device Meeting (IEDM) and 7 papers in IEEE Symposium on VLSI Technology (VLSI) in the past 10 years.

Invited Talk Topic: Reliability and Characterization of GeSe OTS Selector Device

Selector device with high on-state current, high half-bias nonlinearity and excellent endurance is critical to suppress the sneak path in high-density cross-point resistive switching memory arrays. Based on novel characterization and supported by first-principles simulations, filamentary-type switching, Weibull distribution of time-to-switch-on/-off and Vth relaxation in GexSe1-x OTS selector device are demonstrated and associated with defect delocalization/localization. Its endurance degradation and recovery mechanisms are identified as delocalized slow defects accumulation and Ge-Se segregation/crystallization. An optimal refreshing scheme is designed that can improve the endurance by more than five orders. This work provides new insights to the OTS switching, relaxation and degradation mechanisms and guidance for performance improvement.

Professor Xing Wu

Prof. Xing Wu received her bachelor’s degree in Electronic Engineering from Xi’an Jiaotong University (XJTU) China in 2008 and her PhD degree from Nanyang Technological University (NTU) Singapore in 2012 (supervisor: Prof. Kinleong Pey). Then, she worked at the Singapore University of Design and Technology (SUTD) and Southeast University (SEU). She is currently a professor at East China Normal University (ECNU) China. She has published more than 90 SCI journal papers including Nature Communications, Advanced Materials, and IEEE TED with more than 3000 citations. She holds more than 30 patents.

Invited Talk Topic: ESD failure analysis by using transmission electron microscopy at the atomic scale

Transmission electron microscopy (TEM), with its high spatial resolution and versatile external fields, is undoubtedly a powerful tool for the static characterization and dynamic manipulation of nanomaterials and nanodevices at the atomic scale. The rapid development of thin-film and precision microelectromechanical systems (MEMS) techniques allows the microstructure during ESD to be probed and engineered inside TEM under external stimuli such as electrical and thermal fields at the nanoscale. Here, taking advantage of advanced in situ transmission electron microscopy, we manipulated interfaces of ESD. The progress of the in situ TEM paves the way to future nanodevices.