Tutorials

Speakers

Dr. Andrew Kim

Andrew Kim is a senior staff at CMOS reliability R/D team of NSG (Non-volatile memory Solutions Group), Intel Corporation, Folsom, CA, USA. His current focus is BEOL reliability of Cu interconnects. He served as a chair/vice-chair of Dielectric Committee of IRPS2019/2018. Since 1998, he has been working on semiconductor interconnect reliability, BEOL process integration, eFuse design/reliability, TCAD on strained silicon, CMP modeling at various companies (IBM, Samsung and Texas Instruments), gas turbine design and system reliability team at General Electric. He received a B.S. with a minor in Mathematics in 1995 from California State University, Fullerton, CA, M.S. and Ph.D., respectively in 1996 and 2001, from Rensselaer Polytechnic Institute, Troy, NY, all in Mechanical Engineering.

Tutorial Topic: BEOL Reliability Tutorial

BEOL (Back-End-Of-Line) interconnect reliability has always been a critical part of advanced semiconductor technology development and qualifications. The key wear-out failure mechanisms include Electro-Migration (EM), Stress-Migration (SM), Thermal-Cycle (TC), inter-/intra-metal Time-Dependent Dielectric Breakdown (TDDB). In this tutorial, physical descriptions and fundamental understanding of the mechanisms will be discussed, along with electrical characterization methods commonly and sometimes specially applied to BEOL interconnects. Self-heating in interconnects will also be discussed for the brief discussion on Irms (Root-Mean-Square) and Ipeak (max. allowed peak current) for metal wires. Reliability engineers in their early career and non-BEOL-reliability colleagues are strongly encouraged to attend.

Dr. Franco Stellari

Franco Stellari (S’95–M’04-SM’06) received the M.S. degree (summa cum laude) and the Ph.D. degree in electronics engineering from the Politecnico di Milano, Milan, Italy, in 1998 and 2002 respectively. He subsequently joined the IBM T.J. Watson Research Center in Yorktown Heights, NY as a post-doc, becoming a permanent Research Staff Member in 2004. His major interest is the development and use of new optical techniques for testing VLSI circuits based on static imaging, time resolved emission and laser based techniques. During the years he has worked with single-photon detectors with fast response time and very high quantum efficiency, such as InGaAs Single Photon Avalanche Diodes (SPADs) and Superconducting Single Photon Detectors (SSPD), pushing their limits towards record low voltage applications. In 1999 he developed a model of the transistor emission that is still currently used for estimating luminescence from electric circuits. He has also developed a novel methodology for studying latch-up ignition, process variability, power supply noise measurement, and signal integrity. More recently, he has worked on fully exploiting the Light Emission from Off-State Leakage Current (LEOSLC) to developed novel techniques for VLSI circuit testing and hardware security such as chip alterations detection, and logic state mapping, chip reverse engineering, etc. His work leverages the development of automated data collection, advanced analysis, image processing, and computer vision for signal isolation and data extraction. He has more than 100 international publications, more than 45 granted patents. Some of his work in the field of advanced detectors was recognized with the Paul F. Forman Team Engineering Excellence Award in 2015. He was also the recipient of the IEEE EDS Paul Rappaport Award for the best Trans. on Electron Devices of 2004, the Best Poster Award at the International Symposium for Test and Failure Analysis (ISTFA) in 2014, and the Best Paper Award at the European Symposium on Reliability of Electron Devices, Failure Physics and Analysis (ESREF) twice, in 2002 and 2004.

Tutorial Topic: Faster fault isolation with advanced data analysis and computer vision

Advance automated data analysis systems are needed to increase the volume and complexity of image processing required to keep pace with the continuous scaling of technology nodes, and often insufficient sensitivity and resolution of the imaging systems. In particular, measurement automation (such as navigation, focusing, data collection, etc.), as well as computer vision analysis of the data (filtering, segmentation, feature extraction, etc.) are indispensable tools to increase the fault localization success rate and the tool throughput. In this tutorial, we will review the fundamentals and applications of several techniques that may impact different types of imaging systems acquiring pattern images, time-integrated or time-resolved emission, and laser-based images.

Dr. Umberto Celano

Umberto Celano is a Senior Scientist at imec (Belgium), with expertise in materials analysis for semiconductor technology, device physics and nanoscale functional materials. He received his Ph.D. in Physics from the University of Leuven – KU Leuven (Belgium) in 2015. His research has established a novel three-dimensional nanoscale imaging technique that combines sensing with sub-nm material removal to study materials in confined volumes. Currently, Dr. Celano’s research interests encompass nanoelectronics, nanophotonic, functional materials and VLSI metrology. In these areas, he conducted research in various institutions including KU Leuven, Osaka University and Stanford University.

Umberto is the recipient of the Rogen A. Haken Best Paper Award at IEDM (2013) and has authored or co-authored 60+ papers in international journals and conference proceedings. He is part of the metrology working group for the International Roadmap for Devices and Systems (IRDS) and acted as member of the early carrier editorial board of Nano Letters. Previously, Umberto received his B.Eng. in Electronic Engineering and a M.Sc. degree in Nanoelectronics with honors from the University of Rome Sapienza, Italy.”

Tutorial Topic: Scanning Probe Microscopies for Correlative Analysis of Advanced Technology Nodes

Next generation nanoelectronics for logic and memory are based on devices increasingly smaller, more three-dimensional in shape and containing even more types of materials. Therefore, the evaluation of nanometre-scale materials properties, including carrier profiling, strain, electrical and chemical sensing, becomes essential for a deep interpretation of device’s functionalities. Here, I will present the broad role played by scanning probe microscopies as two- and three-dimensional analysis methods in the development of advanced integrated circuits. First, the field will be reviewed with emphasis on the main techniques that offer important applications in nanoelectronics. This will be followed by the introduction of emerging methods for two- and three-dimensional analysis of materials properties in confined volumes. Afterward, I will present a series of real-case studies where we merge materials characterization with correlative and site-specific analysis for process development, integration and metrology of advanced fin-based CMOS nodes. Finally, for the exploration of emerging device concepts, I will showcase applications in the realm of 2D materials and various types of non-volatile memories including ferroelectric and resistive switching.

Professor Christian Boit

Prof. Christian Boit retired 2018 from Chair of Semiconductor Devices Department at Technische Universitaet Berlin, Germany. His research focuses on IC failure analysis (FA) and contactless fault isolation (CFI). In recent years, he was also investigating hardware security risks introduced by CFI. Chris started at Siemens Semiconductors 1986 and participated 1990 -1993 in IBM / Siemens DRAM project East Fishkill, NY. Later, he was Director of FA at Infineon Technologies until taking the university position in 2002. Chris is an active supporter of the FA community. He was co-founder of EDFAS and General Chair of ISTFA 2002 and ESREF 2014.

Tutorial Topic: Contactless Fault Isolation Techniques and IC Hardware Security

Contactless Fault Isolation Techniques like Photon Emission, Laser Stimulation inducing Delay Variation and/or Electro-optical probing have been very powerful to track almost each signal in Integrated Circuits. This enormous success can become a risk for hardware security, if these techniques are applied for attacks on sensitive data.
This tutorial presents hardware security concepts like Physically unclonable Functions (PUFs), gives an overview of hardware security attacks and proposes a risk assessment of CFI based attacking. The chance of protection concepts and countermeasures will also be a topic of the tutorial.

Professor Tan Chuan Seng

Professor Chuan Seng Tan received his BEng degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his MEng degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure) and in September 2019, he was promoted to the rank of full professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He provides his service as committee member for International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, IEEE-EDTM, IEEE-GFP and ECS-Wafer Bonding. He is an associate editor for Elsevier Microelectronics Journal (MEJ) and IEEE Transactions on Components, Packaging and Manufacturing Technology. He is a senior member of IEEE and a recipient of the 2019 Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS). Beginning in June 2019, he serves as a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019.

Tutorial Topic: 3D IC Process Technology – Drivers, Technology Platforms, Challenges & Solutions

The main objective of this course is to allow the attendees to appreciate the role of advanced packaging in IC manufacturing and understand the need for various types of packaging. In preparation for future trends and needs, the bulk of this course will focus on emerging topics in 3D packaging and the role of through silicon via (TSV). Silicon interposer based 2.5D packaging is also discussed, as well as fan-out packaging and monolithic integration. Upon successful completion of the course, attendees are expected to have a better understanding of enabling technology in emerging 2.5D/3D packaging and related applications.