Professor Tan Chuan Seng

Professor Chuan Seng Tan received his BEng degree in electrical engineering from University of Malaya, Malaysia, in 1999. Subsequently, he completed his MEng degree in advanced materials from the National University of Singapore under the Singapore-MIT Alliance (SMA) program in 2001. He then joined the Institute of Microelectronics, Singapore, as a research engineer where he worked on process integration of strained-Si/relaxed-SiGe heterostructure devices. In the fall of 2001, he began his doctoral work at the Massachusetts Institute of Technology, Cambridge, USA, and was awarded a Ph.D. degree in electrical engineering in 2006. He was the recipient of the Applied Materials Graduate Fellowship for 2003-2005. In 2003, he spent his summer interning at Intel Corporation, Oregon. He joined NTU in 2006 as a Lee Kuan Yew Postdoctoral Fellow and since July 2008, he was a holder of the inaugural Nanyang Assistant Professorship. In March 2014, he was promoted to the rank of Associate Professor (with tenure) and in September 2019, he was promoted to the rank of full professor. His research interests are semiconductor process technology and device physics. Currently he is working on process technology of three-dimensional integrated circuits (3-D ICs), as well as engineered substrate (Si/Ge/Sn) for group-IV photonics. He has numerous publications (journal and conference) and IPs on 3-D technology and engineered substrates. Nine of his inventions have since been licensed to a spin-off company. He co-edited/co-authored five books on 3D packaging technology. He provides his service as committee member for International Conference on Wafer Bonding, IEEE-3DIC, IEEE-EPTC, IEEE-ECTC, IEEE-EDTM, IEEE-GFP and ECS-Wafer Bonding. He is an associate editor for Elsevier Microelectronics Journal (MEJ) and IEEE Transactions on Components, Packaging and Manufacturing Technology. He is a senior member of IEEE and a recipient of the 2019 Exceptional Technical Achievement Award from the IEEE Electronics Packaging Society (EPS). Beginning in June 2019, he serves as a Distinguished Lecturer with IEEE-EPS. He is a Fellow of the International Microelectronics Assembly and Packaging Society (IMAPS) since 2019.

Invited Talk Topic: 3D MIM Capacitor Embedded in TSV: A novel on-chip integrated capacitor

In this work, a novel integrated capacitor, called “3D MIM Capacitor Embedded in TSV” is proposed, designed, fabricated, and characterized for application in integrated circuits (ICs) with through-silicon vias (TSVs). A significant capacitance density enhancement can be achieved for this 3D embedded capacitor, because it leverages on the high aspect ratio structure of TSVs. Compared to conventional trench capacitor, this technology does not consume additional silicon area because it is embedded in the trenches of existing TSVs, instead of dedicated trenches. An ultrahigh capacitance density of 5,621.8 nF/mm2 was envisioned according to our model, which is ~13× of 440.0 nF/mm2 from a conventional trench capacitor with the same design parameters. A leakage current density as low as 1.61×10-7 A/cm2 at 4.3V and a breakdown voltage greater than 9.5 V were measured for a sample with a capacitance density of 3,776.6 nF/mm2. In addition, the reliability of the 3D MIM and potential new applications it enables are discussed.